From 1ed997445d317ddfdf5f35cde160123f26a58689 Mon Sep 17 00:00:00 2001 From: momo5502 Date: Sun, 6 Apr 2025 20:17:39 +0200 Subject: [PATCH] Fix IRETQ instruction --- src/icicle/data/Ghidra/Processors/x86/data/languages/ia.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/icicle/data/Ghidra/Processors/x86/data/languages/ia.sinc b/src/icicle/data/Ghidra/Processors/x86/data/languages/ia.sinc index 19edb19c..26dfefa2 100644 --- a/src/icicle/data/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/src/icicle/data/Ghidra/Processors/x86/data/languages/ia.sinc @@ -2866,7 +2866,7 @@ enterFrames: low5 is low5 { tmp:1 = low5; export tmp; } :IRETD is vexMode=0 & addrsize=1 & opsize=1 & byte=0xcf { pop44(EIP); tmp:4=0; pop44(tmp); CS=tmp(0); pop44(eflags); return [EIP]; } @ifdef IA64 :IRETD is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0xcf { pop84(EIP); RIP=zext(EIP); tmp:4=0; pop84(tmp); CS=tmp(0); pop84(eflags); return [RIP]; } -:IRETQ is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xcf { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); pop88(rflags); return [RIP]; } +:IRETQ is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xcf { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); pop88(rflags); pop88(RSP); return [RIP]; } @endif :J^cc rel8 is vexMode=0 & row=7 & cc; rel8 { if (cc) goto rel8; }