Lightemerald/windows-user-space-emulator
2
0
Fork 0
mirror of https://github.com/momo5502/emulator.git synced 2026-01-18 11:13:57 +00:00
Code Issues Packages Projects Releases Wiki Activity

Integrate icicle into CI (#179)

Browse Source 
But disable it for now
This commit is contained in:
Maurice Heumann
2025-04-05 09:23:01 +02:00
committed by GitHub
parent 6b6d2d29f7 dd7a80a9f0
commit 8935a3d56e
56 changed files with 20799 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
.github/workflows/build.yml vendored
View File

@@ -268,6 +268,9 @@ jobs:
- Linux x86_64 Clang
- macOS arm64
- macOS x86_64
emulator:
- Unicorn
#- Icicle
emulation-root:
- Windows 2025
- Windows 2022
@@ -299,9 +302,10 @@ jobs:
submodules: recursive
- name: Setup Environment Variables
if: ${{ contains(matrix.platform, 'Sanitizer') }}
run: |
echo "RUST_BACKTRACE=1" >> $GITHUB_ENV
echo "ASAN_OPTIONS=detect_odr_violation=0" >> $GITHUB_ENV
echo "EMULATOR_ICICLE=${{ matrix.emulator == 'Icicle' }}" >> $GITHUB_ENV
- name: Download Test Configuration
uses: actions/download-artifact@v4.2.1
@@ -348,6 +352,9 @@ jobs:
architecture:
- x86_64
#- arm64-v8a
emulator:
- Unicorn
#- Icicle
emulation-root:
- Windows 2025
- Windows 2022
@@ -398,7 +405,7 @@ jobs:
with:
api-level: 29
arch: ${{matrix.architecture}}
script: "adb push build/${{matrix.preset}}/artifacts/* /data/local/tmp && adb shell \"cd /data/local/tmp && export LD_LIBRARY_PATH=. && chmod +x ./analyzer && ./analyzer -e ./root c:/test-sample.exe\""
script: "adb push build/${{matrix.preset}}/artifacts/* /data/local/tmp && adb shell \"cd /data/local/tmp && export LD_LIBRARY_PATH=. && chmod +x ./analyzer && EMULATOR_ICICLE=${{ matrix.emulator == 'Icicle' }} ./analyzer -e ./root c:/test-sample.exe\""
summary:
name: Pipeline Summary

4
src/emulator/memory_interface.hpp
View File

@@ -4,8 +4,8 @@
#include "memory_permission.hpp"
using mmio_read_callback = std::function<uint64_t(uint64_t addr, size_t size)>;
using mmio_write_callback = std::function<void(uint64_t addr, size_t size, uint64_t data)>;
using mmio_read_callback = std::function<void(uint64_t addr, void* data, size_t size)>;
using mmio_write_callback = std::function<void(uint64_t addr, const void* data, size_t size)>;
class memory_manager;

29
src/icicle-emulator/icicle_x64_emulator.cpp
View File

@@ -12,8 +12,8 @@ extern "C"
using violation_func = int32_t(void*, uint64_t address, uint8_t operation, int32_t unmapped);
using data_accessor_func = void(void* user, const void* data, size_t length);
using icicle_mmio_read_func = void(void* user, uint64_t address, size_t length, void* data);
using icicle_mmio_write_func = void(void* user, uint64_t address, size_t length, const void* data);
using icicle_mmio_read_func = void(void* user, uint64_t address, void* data, size_t length);
using icicle_mmio_write_func = void(void* user, uint64_t address, const void* data, size_t length);
icicle_emulator* icicle_create_emulator();
int32_t icicle_protect_memory(icicle_emulator*, uint64_t address, uint64_t length, uint8_t permissions);
@@ -185,31 +185,14 @@ namespace icicle
auto* ptr = wrapper.get();
this->storage_.push_back(std::move(wrapper));
auto* read_wrapper = +[](void* user, const uint64_t addr, const size_t length, void* data) {
constexpr auto limit = sizeof(uint64_t);
auto* read_wrapper = +[](void* user, const uint64_t addr, void* data, const size_t length) {
const auto* w = static_cast<mmio_wrapper*>(user);
// TODO: Change interface to get rid of loop
for (size_t offset = 0; offset < length; offset += limit)
{
const auto max_read = std::min(limit, length - offset);
const auto value = w->read_cb(addr + offset - w->base, max_read);
memcpy(static_cast<uint8_t*>(data) + offset, &value, max_read);
}
w->read_cb(addr - w->base, data, length);
};
auto* write_wrapper = +[](void* user, const uint64_t addr, const size_t length, const void* data) {
constexpr auto limit = sizeof(uint64_t);
auto* write_wrapper = +[](void* user, const uint64_t addr, const void* data, const size_t length) {
const auto* w = static_cast<mmio_wrapper*>(user);
// TODO: Change interface to get rid of loop
for (size_t offset = 0; offset < length; offset += limit)
{
uint64_t value{};
const auto max_read = std::min(limit, length - offset);
memcpy(&value, static_cast<const uint8_t*>(data) + offset, max_read);
w->write_cb(addr + offset - w->base, max_read, value);
}
w->write_cb(addr + w->base, data, length);
};
icicle_map_mmio(this->emu_, address, size, read_wrapper, ptr, write_wrapper, ptr);

6
src/icicle/CMakeLists.txt
View File

@@ -45,6 +45,12 @@ ExternalProject_Add(
BUILD_BYPRODUCTS ${ICICLE_RUST_LIB}
)
add_custom_command(
TARGET icicle-rust-project POST_BUILD
COMMAND ${CMAKE_COMMAND} -E copy_directory "${CMAKE_CURRENT_LIST_DIR}/data" "${CMAKE_LIBRARY_OUTPUT_DIRECTORY}"
COMMENT "Copying Ghidra Processor Specification"
)
add_library(icicle INTERFACE)
add_dependencies(icicle icicle-rust-project)
target_link_libraries(icicle INTERFACE ${ICICLE_RUST_LIB})

33
src/icicle/data/Ghidra/Processors/x86/data/languages/adx.sinc Normal file
View File

@@ -0,0 +1,33 @@
:ADCX Reg32, rm32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF6; rm32 & Reg32 ... & check_Reg32_dest ... {
tmp:5 = zext(Reg32) + zext(rm32) + zext(CF);
tmpCF:1 = tmp(4); # just the carry byte
CF = tmpCF != 0;
Reg32 = tmp:4;
build check_Reg32_dest;
}
@ifdef IA64
:ADCX Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF6; Reg64 ... & rm64 {
tmp:9 = zext(Reg64) + zext(rm64) + zext(CF);
tmpCF:1 = tmp(8); # just the carry byte
CF = tmpCF != 0;
Reg64 = tmp:8;
}
@endif
:ADOX Reg32, rm32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF6; rm32 & Reg32 ... & check_Reg32_dest ... {
tmp:5 = zext(Reg32) + zext(rm32) + zext(OF);
tmpOF:1 = tmp(4); # just the carry byte
OF = tmpOF != 0;
Reg32 = tmp:4;
build check_Reg32_dest;
}
@ifdef IA64
:ADOX Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF6; Reg64 ... & rm64 {
tmp:9 = zext(Reg64) + zext(rm64) + zext(OF);
tmpOF:1 = tmp(8); # just the carry byte
OF = tmpOF != 0;
Reg64 = tmp:8;
}
@endif

3275
src/icicle/data/Ghidra/Processors/x86/data/languages/avx.sinc Normal file
View File

File diff suppressed because it is too large Load Diff

1221
src/icicle/data/Ghidra/Processors/x86/data/languages/avx2.sinc Normal file
View File

File diff suppressed because it is too large Load Diff

252
src/icicle/data/Ghidra/Processors/x86/data/languages/avx2_manual.sinc Normal file
View File

@@ -0,0 +1,252 @@
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109785
define pcodeop vinserti128 ;
:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0 {
local tmp:16 = XmmReg2_m128;
# ignoring all but the least significant bit
if (imm8_0:1 == 0) goto <case0>;
if (imm8_0:1 == 1) goto <case1>;
<case0>
YmmReg1[0,128] = tmp;
YmmReg1[128,128] = vexVVVV_YmmReg[128,128];
goto <done>;
<case1>
YmmReg1[0,128] = vexVVVV_YmmReg[0,128];
YmmReg1[128,128] = tmp;
<done>
}
# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106903
define pcodeop vgatherdpd ;
:VGATHERDPD XmmReg1, q_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x92; (XmmReg1 & YmmReg1) ... & q_vm32x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vgatherdpd(XmmReg1, q_vm32x, vexVVVV_XmmReg);
local tmp:16 = vgatherdpd(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106908
@ifdef IA64
define pcodeop vgatherqpd ;
:VGATHERQPD XmmReg1, q_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & YmmReg1) ... & q_vm64x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vgatherqpd(XmmReg1, q_vm64x, vexVVVV_XmmReg);
local tmp:16 = vgatherqpd(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
@endif
# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106913
:VGATHERDPD YmmReg1, q_vm32x, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x92; YmmReg1 ... & q_vm32x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# YmmReg1 = vgatherdpd(YmmReg1, q_vm32x, vexVVVV_YmmReg);
YmmReg1 = vgatherdpd(YmmReg1, vexVVVV_YmmReg);
# TODO ZmmReg1 = zext(YmmReg1)
vexVVVV_YmmReg = 0;
}
# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106918
@ifdef IA64
:VGATHERQPD YmmReg1, q_vm64y, vexVVVV_YmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x93; YmmReg1 ... & q_vm64y {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# YmmReg1 = vgatherqpd(YmmReg1, q_vm64y, vexVVVV_YmmReg);
YmmReg1 = vgatherqpd(YmmReg1, vexVVVV_YmmReg);
# TODO ZmmReg1 = zext(YmmReg1)
vexVVVV_YmmReg = 0;
}
@endif
# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107130
define pcodeop vgatherdps ;
:VGATHERDPS XmmReg1, d_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x92; (XmmReg1 & YmmReg1) ... & d_vm32x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vgatherdps(XmmReg1, d_vm32x, vexVVVV_XmmReg);
local tmp:16 = vgatherdps(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107135
@ifdef IA64
define pcodeop vgatherqps ;
:VGATHERQPS XmmReg1, d_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & YmmReg1) ... & d_vm64x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vgatherqps(XmmReg1, d_vm64x, vexVVVV_XmmReg);
local tmp:16 = vgatherqps(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
@endif
# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107140
:VGATHERDPS YmmReg1, d_vm32y, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x92; YmmReg1 ... & d_vm32y {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# YmmReg1 = vgatherdps(YmmReg1, d_vm32y, vexVVVV_YmmReg);
YmmReg1 = vgatherdps(YmmReg1, vexVVVV_YmmReg);
# TODO ZmmReg1 = zext(YmmReg1)
vexVVVV_YmmReg = 0;
}
# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107145
@ifdef IA64
:VGATHERQPS XmmReg1, d_vm64y, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & YmmReg1) ... & d_vm64y {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vgatherqps(XmmReg1, d_vm64y, vexVVVV_XmmReg);
XmmReg1 = vgatherqps(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(XmmReg1);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
@endif
# PCMPEQQ 4-250 PAGE 1370 LINE 71171
:VPCMPEQQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x29; YmmReg1 ... & YmmReg2_m256
{
YmmReg1[0,64] = zext(vexVVVV_YmmReg[0,64] == YmmReg2_m256[0,64]) * 0xffffffffffffffff:8;
YmmReg1[64,64] = zext(vexVVVV_YmmReg[64,64] == YmmReg2_m256[64,64]) * 0xffffffffffffffff:8;
YmmReg1[128,64] = zext(vexVVVV_YmmReg[128,64] == YmmReg2_m256[128,64]) * 0xffffffffffffffff:8;
YmmReg1[192,64] = zext(vexVVVV_YmmReg[192,64] == YmmReg2_m256[192,64]) * 0xffffffffffffffff:8;
# TODO ZmmReg1 = zext(YmmReg1)
}
# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107884
define pcodeop vpgatherdd ;
:VPGATHERDD XmmReg1, d_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x90; (XmmReg1 & YmmReg1) ... & d_vm32x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vpgatherdd(XmmReg1, d_vm32x, vexVVVV_XmmReg);
local tmp:16 = vpgatherdd(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107888
@ifdef IA64
define pcodeop vpgatherqd ;
:VPGATHERQD XmmReg1, d_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & YmmReg1) ... & d_vm64x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vpgatherqd(XmmReg1, d_vm64x, vexVVVV_XmmReg);
local tmp:16 = vpgatherqd(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
@endif
# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107892
:VPGATHERDD YmmReg1, d_vm32y, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x90; YmmReg1 ... & d_vm32y {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# YmmReg1 = vpgatherdd(YmmReg1, d_vm32y, vexVVVV_YmmReg);
YmmReg1 = vpgatherdd(YmmReg1, vexVVVV_YmmReg);
# TODO ZmmReg1 = zext(YmmReg1)
vexVVVV_YmmReg = 0;
}
# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107896
@ifdef IA64
:VPGATHERQD XmmReg1, d_vm64y, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & YmmReg1) ... & d_vm64y {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vpgatherqd(XmmReg1, d_vm64y, vexVVVV_XmmReg);
local tmp:16 = vpgatherqd(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
@endif
# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108234
define pcodeop vpgatherdq ;
:VPGATHERDQ XmmReg1, q_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x90; (XmmReg1 & YmmReg1) ... & q_vm32x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vpgatherdq(XmmReg1, q_vm32x, vexVVVV_XmmReg);
local tmp:16 = vpgatherdq(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108238
@ifdef IA64
define pcodeop vpgatherqq ;
:VPGATHERQQ XmmReg1, q_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & YmmReg1) ... & q_vm64x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# XmmReg1 = vpgatherqq(XmmReg1, q_vm64x, vexVVVV_XmmReg);
local tmp:16 = vpgatherqq(XmmReg1, vexVVVV_XmmReg);
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
vexVVVV_XmmReg = 0;
}
@endif
# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108242
:VPGATHERDQ YmmReg1, q_vm32x, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x90; YmmReg1 ... & q_vm32x {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# YmmReg1 = vpgatherdq(YmmReg1, q_vm32x, vexVVVV_YmmReg);
YmmReg1 = vpgatherdq(YmmReg1, vexVVVV_YmmReg);
# TODO ZmmReg1 = zext(YmmReg1)
vexVVVV_YmmReg = 0;
}
# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108246
@ifdef IA64
:VPGATHERQQ YmmReg1, q_vm64y, vexVVVV_YmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x91; YmmReg1 ... & q_vm64y {
# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
# YmmReg1 = vpgatherqq(YmmReg1, q_vm64y, vexVVVV_YmmReg);
YmmReg1 = vpgatherqq(YmmReg1, vexVVVV_YmmReg);
# TODO ZmmReg1 = zext(YmmReg1)
vexVVVV_YmmReg = 0;
}
@endif
# PMOVMSKB 4-338 PAGE 1458 LINE 75655
:VPMOVMSKB Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & YmmReg2) & check_Reg32_dest
{
local byte_mask:4 = 0:4;
byte_mask[0,1] = YmmReg2[7,1];
byte_mask[1,1] = YmmReg2[15,1];
byte_mask[2,1] = YmmReg2[23,1];
byte_mask[3,1] = YmmReg2[31,1];
byte_mask[4,1] = YmmReg2[39,1];
byte_mask[5,1] = YmmReg2[47,1];
byte_mask[6,1] = YmmReg2[55,1];
byte_mask[7,1] = YmmReg2[63,1];
byte_mask[8,1] = YmmReg2[71,1];
byte_mask[9,1] = YmmReg2[79,1];
byte_mask[10,1] = YmmReg2[87,1];
byte_mask[11,1] = YmmReg2[95,1];
byte_mask[12,1] = YmmReg2[103,1];
byte_mask[13,1] = YmmReg2[111,1];
byte_mask[14,1] = YmmReg2[119,1];
byte_mask[15,1] = YmmReg2[127,1];
byte_mask[16,1] = YmmReg2[135,1];
byte_mask[17,1] = YmmReg2[143,1];
byte_mask[18,1] = YmmReg2[151,1];
byte_mask[19,1] = YmmReg2[159,1];
byte_mask[20,1] = YmmReg2[167,1];
byte_mask[21,1] = YmmReg2[175,1];
byte_mask[22,1] = YmmReg2[183,1];
byte_mask[23,1] = YmmReg2[191,1];
byte_mask[24,1] = YmmReg2[199,1];
byte_mask[25,1] = YmmReg2[207,1];
byte_mask[26,1] = YmmReg2[215,1];
byte_mask[27,1] = YmmReg2[223,1];
byte_mask[28,1] = YmmReg2[231,1];
byte_mask[29,1] = YmmReg2[239,1];
byte_mask[30,1] = YmmReg2[247,1];
byte_mask[31,1] = YmmReg2[255,1];
Reg32 = zext(byte_mask);
build check_Reg32_dest;
}

287
src/icicle/data/Ghidra/Processors/x86/data/languages/avx_manual.sinc Normal file
View File

@@ -0,0 +1,287 @@
# MOVAPD 4-45 PAGE 1165 LINE 60844
:VMOVAPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x28; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
YmmReg1 = zext(XmmReg2_m128);
# TODO ZmmReg1 = zext(XmmReg1)
}
# MOVAPD 4-45 PAGE 1165 LINE 60846
:VMOVAPD XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; mod=3 & XmmReg1 & (XmmReg2 & YmmReg2)
{
YmmReg2 = zext(XmmReg1);
# TODO ZmmReg2 = zext(XmmReg2)
}
# MOVAPD 4-45 PAGE 1165 LINE 60846
:VMOVAPD m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; XmmReg1 ... & m128
{
m128 = XmmReg1;
# TODO ZmmReg2 = zext(XmmReg2)
}
# MOVAPD 4-45 PAGE 1165 LINE 60848
:VMOVAPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x28; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = YmmReg2_m256;
# TODO ZmmReg1 = zext(YmmReg1)
}
# MOVAPD 4-45 PAGE 1165 LINE 60850
:VMOVAPD YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; YmmReg1 ... & YmmReg2_m256
{
YmmReg2_m256 = YmmReg1;
# TODO ZmmReg2 = zext(YmmReg2)
}
# MOVAPS 4-49 PAGE 1169 LINE 61039
:VMOVAPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x28; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
YmmReg1 = zext(XmmReg2_m128);
# TODO ZmmReg1 = zext(XmmReg1)
}
# MOVAPS 4-49 PAGE 1169 LINE 61041
:VMOVAPS XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; mod=3 & XmmReg1 & (XmmReg2 & YmmReg2)
{
YmmReg2 = zext(XmmReg1);
# TODO ZmmReg2 = zext(XmmReg2)
}
# MOVAPS 4-49 PAGE 1169 LINE 61041
:VMOVAPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; XmmReg1 ... & m128
{
m128 = XmmReg1;
# TODO ZmmReg2 = zext(XmmReg2)
}
# MOVAPS 4-49 PAGE 1169 LINE 61043
:VMOVAPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x28; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = YmmReg2_m256;
# TODO ZmmReg1 = zext(YmmReg1)
}
# MOVAPS 4-49 PAGE 1169 LINE 61045
:VMOVAPS YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; YmmReg1 ... & YmmReg2_m256
{
YmmReg2_m256 = YmmReg1;
# TODO ZmmReg2 = zext(YmmReg2)
}
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61667
# Note: we do not model the exception generated if VMOVDQA is used with a memory operand which is not 16-bye aligned
:VMOVDQA XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
YmmReg1 = zext(XmmReg2_m128);
# TODO ZmmReg1 = zext(XmmReg1)
}
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669
:VMOVDQA XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 & (mod = 3 & XmmReg2 & YmmReg2)
{
YmmReg2 = zext(XmmReg1);
# TODO ZmmReg2 = zext(XmmReg2)
}
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669
:VMOVDQA m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 ... & m128
{
m128 = XmmReg1;
# TODO ZmmReg2 = zext(XmmReg2)
}
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61671
:VMOVDQA YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = YmmReg2_m256;
# TODO ZmmReg1 = zext(YmmReg1)
}
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61673
:VMOVDQA YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 ... & YmmReg2_m256
{
YmmReg2_m256 = YmmReg1;
# TODO ZmmReg2 = zext(YmmReg2)
}
# MOVSD 4-111 PAGE 1231 LINE 63970
:VMOVSD XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x10; XmmReg1 & YmmReg1 & (mod=0x3 & XmmReg2)
{
local tmpa:8 = XmmReg2[0,64];
local tmpb:8 = vexVVVV_XmmReg[64,64];
YmmReg1 = 0;
XmmReg1[0,64] = tmpa;
XmmReg1[64,64] = tmpb;
# TODO ZmmReg1 = zext(XmmReg1)
}
# MOVSD 4-111 PAGE 1231 LINE 63972
:VMOVSD XmmReg1, m64 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1) ... & m64
{
YmmReg1[0,64] = m64;
YmmReg1[64,64] = 0;
# TODO ZmmReg1 = zext(XmmReg1)
}
# MOVSD 4-111 PAGE 1231 LINE 63974
:VMOVSD XmmReg2, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & YmmReg2))
{
local tmpa:8 = XmmReg1[0,64];
local tmpb:8 = vexVVVV_XmmReg[64,64];
YmmReg2 = 0;
XmmReg2[0,64] = tmpa;
XmmReg2[64,64] = tmpb;
# TODO ZmmReg2 = zext(XmmReg2)
}
# MOVSD 4-111 PAGE 1231 LINE 63976
:VMOVSD m64, XmmReg1 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m64
{
m64 = XmmReg1[0,64];
}
# MOVUPS 4-130 PAGE 1250 LINE 64872
:VMOVUPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = XmmReg2_m128;
YmmReg1[0,128] = tmp;
YmmReg1[128,64] = 0;
YmmReg1[192,64] = 0;
}
# MOVUPS 4-130 PAGE 1250 LINE 64874
# break this into two constructors to handle the zext for the register destination case
:VMOVUPS XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 & (mod = 3 & XmmReg2 & YmmReg2)
{
XmmReg2 = XmmReg1;
YmmReg2 = zext(XmmReg2);
}
# MOVUPS 4-130 PAGE 1250 LINE 64874
:VMOVUPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m128
{
m128 = XmmReg1;
}
# MOVUPS 4-130 PAGE 1250 LINE 64876
:VMOVUPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x10; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = YmmReg2_m256;
# TODO ZmmReg1 = zext(YmmReg1)
}
# MOVUPS 4-130 PAGE 1250 LINE 64878
# TODO in general, what do we do with the zext of only the register case; needs investigation
:VMOVUPS YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; YmmReg1 ... & YmmReg2_m256
{
YmmReg2_m256 = YmmReg1;
}
# PCMPEQQ 4-250 PAGE 1370 LINE 71169
:VPCMPEQQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x29; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1[0,64] = zext(vexVVVV_XmmReg[0,64] == XmmReg2_m128[0,64]) * 0xffffffffffffffff:8;
XmmReg1[64,64] = zext(vexVVVV_XmmReg[64,64] == XmmReg2_m128[64,64]) * 0xffffffffffffffff:8;
YmmReg1 = zext(XmmReg1);
# TODO ZmmReg1 = zext(XmmReg1)
}
# PMOVMSKB 4-338 PAGE 1458 LINE 75651
:VPMOVMSKB Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & XmmReg2) & check_Reg32_dest
{
local byte_mask:2 = 0:2;
byte_mask[0,1] = XmmReg2[7,1];
byte_mask[1,1] = XmmReg2[15,1];
byte_mask[2,1] = XmmReg2[23,1];
byte_mask[3,1] = XmmReg2[31,1];
byte_mask[4,1] = XmmReg2[39,1];
byte_mask[5,1] = XmmReg2[47,1];
byte_mask[6,1] = XmmReg2[55,1];
byte_mask[7,1] = XmmReg2[63,1];
byte_mask[8,1] = XmmReg2[71,1];
byte_mask[9,1] = XmmReg2[79,1];
byte_mask[10,1] = XmmReg2[87,1];
byte_mask[11,1] = XmmReg2[95,1];
byte_mask[12,1] = XmmReg2[103,1];
byte_mask[13,1] = XmmReg2[111,1];
byte_mask[14,1] = XmmReg2[119,1];
byte_mask[15,1] = XmmReg2[127,1];
Reg32 = zext(byte_mask);
build check_Reg32_dest;
}
# VZEROALL 5-563 PAGE 2387 LINE 122405
:VZEROALL is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77
{
YMM0[0,64] = 0:8; YMM0[64,64] = 0:8; YMM0[128,64] = 0:8; YMM0[192,64] = 0:8;
YMM1[0,64] = 0:8; YMM1[64,64] = 0:8; YMM1[128,64] = 0:8; YMM1[192,64] = 0:8;
YMM2[0,64] = 0:8; YMM2[64,64] = 0:8; YMM2[128,64] = 0:8; YMM2[192,64] = 0:8;
YMM3[0,64] = 0:8; YMM3[64,64] = 0:8; YMM3[128,64] = 0:8; YMM3[192,64] = 0:8;
YMM4[0,64] = 0:8; YMM4[64,64] = 0:8; YMM4[128,64] = 0:8; YMM4[192,64] = 0:8;
YMM5[0,64] = 0:8; YMM5[64,64] = 0:8; YMM5[128,64] = 0:8; YMM5[192,64] = 0:8;
YMM6[0,64] = 0:8; YMM6[64,64] = 0:8; YMM6[128,64] = 0:8; YMM6[192,64] = 0:8;
YMM7[0,64] = 0:8; YMM7[64,64] = 0:8; YMM7[128,64] = 0:8; YMM7[192,64] = 0:8;
#TODO: Zmm
}
@ifdef IA64
:VZEROALL is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77
{
YMM0[0,64] = 0:8; YMM0[64,64] = 0:8; YMM0[128,64] = 0:8; YMM0[192,64] = 0:8;
YMM1[0,64] = 0:8; YMM1[64,64] = 0:8; YMM1[128,64] = 0:8; YMM1[192,64] = 0:8;
YMM2[0,64] = 0:8; YMM2[64,64] = 0:8; YMM2[128,64] = 0:8; YMM2[192,64] = 0:8;
YMM3[0,64] = 0:8; YMM3[64,64] = 0:8; YMM3[128,64] = 0:8; YMM3[192,64] = 0:8;
YMM4[0,64] = 0:8; YMM4[64,64] = 0:8; YMM4[128,64] = 0:8; YMM4[192,64] = 0:8;
YMM5[0,64] = 0:8; YMM5[64,64] = 0:8; YMM5[128,64] = 0:8; YMM5[192,64] = 0:8;
YMM6[0,64] = 0:8; YMM6[64,64] = 0:8; YMM6[128,64] = 0:8; YMM6[192,64] = 0:8;
YMM7[0,64] = 0:8; YMM7[64,64] = 0:8; YMM7[128,64] = 0:8; YMM7[192,64] = 0:8;
YMM8[0,64] = 0:8; YMM8[64,64] = 0:8; YMM8[128,64] = 0:8; YMM8[192,64] = 0:8;
YMM9[0,64] = 0:8; YMM9[64,64] = 0:8; YMM9[128,64] = 0:8; YMM9[192,64] = 0:8;
YMM10[0,64] = 0:8; YMM10[64,64] = 0:8; YMM10[128,64] = 0:8; YMM10[192,64] = 0:8;
YMM11[0,64] = 0:8; YMM11[64,64] = 0:8; YMM11[128,64] = 0:8; YMM11[192,64] = 0:8;
YMM12[0,64] = 0:8; YMM12[64,64] = 0:8; YMM12[128,64] = 0:8; YMM12[192,64] = 0:8;
YMM13[0,64] = 0:8; YMM13[64,64] = 0:8; YMM13[128,64] = 0:8; YMM13[192,64] = 0:8;
YMM14[0,64] = 0:8; YMM14[64,64] = 0:8; YMM14[128,64] = 0:8; YMM14[192,64] = 0:8;
YMM15[0,64] = 0:8; YMM15[64,64] = 0:8; YMM15[128,64] = 0:8; YMM15[192,64] = 0:8;
#TODO: Zmm
}
@endif
# VZEROUPPER 5-565 PAGE 2389 LINE 122480
:VZEROUPPER is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77
{
YMM0[128,64] = 0:8; YMM0[192,64] = 0:8;
YMM1[128,64] = 0:8; YMM1[192,64] = 0:8;
YMM2[128,64] = 0:8; YMM2[192,64] = 0:8;
YMM3[128,64] = 0:8; YMM3[192,64] = 0:8;
YMM4[128,64] = 0:8; YMM4[192,64] = 0:8;
YMM5[128,64] = 0:8; YMM5[192,64] = 0:8;
YMM6[128,64] = 0:8; YMM6[192,64] = 0:8;
YMM7[128,64] = 0:8; YMM7[192,64] = 0:8;
#TODO: Zmm
}
@ifdef IA64
:VZEROUPPER is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77
{
YMM0[128,64] = 0:8; YMM0[192,64] = 0:8;
YMM1[128,64] = 0:8; YMM1[192,64] = 0:8;
YMM2[128,64] = 0:8; YMM2[192,64] = 0:8;
YMM3[128,64] = 0:8; YMM3[192,64] = 0:8;
YMM4[128,64] = 0:8; YMM4[192,64] = 0:8;
YMM5[128,64] = 0:8; YMM5[192,64] = 0:8;
YMM6[128,64] = 0:8; YMM6[192,64] = 0:8;
YMM7[128,64] = 0:8; YMM7[192,64] = 0:8;
YMM8[128,64] = 0:8; YMM8[192,64] = 0:8;
YMM9[128,64] = 0:8; YMM9[192,64] = 0:8;
YMM10[128,64] = 0:8; YMM10[192,64] = 0:8;
YMM11[128,64] = 0:8; YMM11[192,64] = 0:8;
YMM12[128,64] = 0:8; YMM12[192,64] = 0:8;
YMM13[128,64] = 0:8; YMM13[192,64] = 0:8;
YMM14[128,64] = 0:8; YMM14[192,64] = 0:8;
YMM15[128,64] = 0:8; YMM15[192,64] = 0:8;
#TODO: Zmm
}
@endif

195
src/icicle/data/Ghidra/Processors/x86/data/languages/bmi1.sinc Normal file
View File

@@ -0,0 +1,195 @@
macro tzcntflags(input, output) {
ZF = (output == 0);
CF = (input == 0);
# OF, SF, PF, AF are undefined
}
####
#### BMI1 instructions
####
# TODO remove ANDN from ia.sinc ?????
:ANDN Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf2; Reg32 ... & check_Reg32_dest ... &rm32
{
Reg32 = ~(vexVVVV_r32) & rm32;
resultflags(Reg32);
OF = 0;
CF = 0;
build check_Reg32_dest;
}
@ifdef IA64
# TODO remove ANDN from ia.sinc ?????
:ANDN Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf2; Reg64 ... & rm64
{
Reg64 = ~(vexVVVV_r64) & rm64;
resultflags(Reg64);
OF = 0;
CF = 0;
}
@endif
:BEXTR Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32
{
sourceTmp:1 = vexVVVV_r32[0,8];
lengthTmp:1 = vexVVVV_r32[8,8];
Reg32 = (rm32 >> sourceTmp) & ((1 << lengthTmp) - 1);
build check_Reg32_dest;
ZF = (Reg32 == 0);
OF = 0;
CF = 0;
# AF, SF, and PF are undefined
}
@ifdef IA64
:BEXTR Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64
{
sourceTmp:1 = vexVVVV_r64[0,8];
lengthTmp:1 = vexVVVV_r64[8,8];
Reg64 = (rm64 >> sourceTmp) & ((1 << lengthTmp) - 1);
ZF = (Reg64 == 0);
OF = 0;
CF = 0;
# AF, SF, and PF are undefined
}
@endif
:BLSI vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=3 ... & check_vexVVVV_r32_dest ... & rm32
{
vexVVVV_r32 = -rm32 & rm32;
build check_vexVVVV_r32_dest;
ZF = (vexVVVV_r32 == 0);
SF = (vexVVVV_r32 s< 0);
CF = (rm32 != 0);
OF = 0;
# AF and PF are undefined
}
@ifdef IA64
:BLSI vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=3 ... & rm64
{
vexVVVV_r64 = -rm64 & rm64;
ZF = (vexVVVV_r64 == 0);
SF = (vexVVVV_r64 s< 0);
CF = (rm64 != 0);
OF = 0;
# AF and PF are undefined
}
@endif
:BLSMSK vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=2 ... & check_vexVVVV_r32_dest ... &rm32
{
CF = (rm32 == 0);
vexVVVV_r32 = (rm32 - 1) ^ rm32;
SF = (vexVVVV_r32 s< 0);
build check_vexVVVV_r32_dest;
ZF = 0;
OF = 0;
# AF and PF are undefined
}
@ifdef IA64
:BLSMSK vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=2 ... & rm64
{
CF = (rm64 == 0);
vexVVVV_r64 = (rm64 - 1) ^ rm64;
SF = (vexVVVV_r64 s< 0);
ZF = 0;
OF = 0;
# AF and PF are undefined
}
@endif
:BLSR vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=1 ... & check_vexVVVV_r32_dest ... &rm32
{
CF = (rm32 == 0);
vexVVVV_r32 = (rm32 - 1) & rm32;
build check_vexVVVV_r32_dest;
ZF = (vexVVVV_r32 == 0);
SF = (vexVVVV_r32 s< 0);
OF = 0;
# AF and PF are undefined
}
@ifdef IA64
:BLSR vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=1 ... & rm64
{
CF = (rm64 == 0);
vexVVVV_r64 = (rm64 - 1) & rm64;
ZF = (vexVVVV_r64 == 0);
SF = (vexVVVV_r64 s< 0);
OF = 0;
# AF and PF are undefined
}
@endif
# not as documented in manual; requires PRE_66 prefix to get 16-bit operation
:TZCNT Reg16, rm16 is vexMode=0 & opsize=0 & $(PRE_66) & $(PRE_F3) & byte=0x0F; byte=0xBC; Reg16 ... & rm16 {
countTmp:2 = 0;
inputTmp:2 = rm16;
<loopbegin>
if ((inputTmp & 1) != 0) goto <loopend>;
countTmp = countTmp + 1;
inputTmp = (inputTmp >> 1) | 0x8000;
goto <loopbegin>;
<loopend>
tzcntflags(rm16, countTmp);
Reg16 = countTmp;
}
:TZCNT Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xBC; Reg32 ... & check_Reg32_dest ... & rm32 {
countTmp:4 = 0;
inputTmp:4 = rm32;
<loopbegin>
if ((inputTmp & 1) != 0) goto <loopend>;
countTmp = countTmp + 1;
inputTmp = (inputTmp >> 1) | 0x80000000;
goto <loopbegin>;
<loopend>
tzcntflags(rm32, countTmp);
Reg32 = countTmp;
build check_Reg32_dest;
}
@ifdef IA64
:TZCNT Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xBC; Reg64 ... & rm64 {
countTmp:8 = 0;
inputTmp:8 = rm64;
<loopbegin>
if ((inputTmp & 1) != 0) goto <loopend>;
countTmp = countTmp + 1;
inputTmp = (inputTmp >> 1) | 0x8000000000000000;
goto <loopbegin>;
<loopend>
tzcntflags(rm64, countTmp);
Reg64 = countTmp;
}
@endif

209
src/icicle/data/Ghidra/Processors/x86/data/languages/bmi2.sinc Normal file
View File

@@ -0,0 +1,209 @@
####
#### BMI2 instructions
####
:BZHI Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32
{
indexTmp:1 = vexVVVV_r32:1;
# saturate index amount to 32; operand size or higher does not clear any bits
shift:1 = (indexTmp <= 32) * (32 - indexTmp);
# clear the upper bits
Reg32 = (rm32 << shift) >> shift;
build check_Reg32_dest;
ZF = (Reg32 == 0);
SF = (Reg32 s< 0);
CF = indexTmp > 31;
OF = 0;
# AF and PF are undefined
}
@ifdef IA64
:BZHI Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64
{
indexTmp:1 = vexVVVV_r64:1;
# saturate index amount to 64; operand size or higher does not clear any bits
shift:1 = (indexTmp <= 64) * (64 - indexTmp);
# clear the upper bits
Reg64 = (rm64 << shift) >> shift;
ZF = (Reg64 == 0);
SF = (Reg64 s< 0);
CF = indexTmp > 63;
OF = 0;
# AF and PF are undefined
}
@endif
:MULX Reg32, vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf6; Reg32 ... & check_Reg32_dest ... & check_vexVVVV_r32_dest ... & rm32
{
temp:8 = zext(EDX) * zext(rm32);
vexVVVV_r32 = temp:4;
build check_vexVVVV_r32_dest;
Reg32 = temp(4);
build check_Reg32_dest;
}
@ifdef IA64
:MULX Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf6; Reg64 ... & rm64
{
temp:16 = zext(RDX) * zext(rm64);
vexVVVV_r64 = temp:8;
Reg64 = temp(8);
}
@endif
:PDEP Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32
{
sourceTmp:4 = vexVVVV_r32;
indexTmp:4 = 1;
resultTmp:4 = 0;
<loop>
maskBit:4 = rm32 & indexTmp;
if (maskBit == 0) goto <nextMaskBit>;
resultTmp = resultTmp | (maskBit * (sourceTmp & 1));
sourceTmp = sourceTmp >> 1;
<nextMaskBit>
indexTmp = indexTmp << 1;
if (indexTmp != 0) goto <loop>;
Reg32 = resultTmp;
build check_Reg32_dest;
}
@ifdef IA64
:PDEP Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64
{
sourceTmp:8 = vexVVVV_r64;
indexTmp:8 = 1;
resultTmp:8 = 0;
<loop>
maskBit:8 = rm64 & indexTmp;
if (maskBit == 0) goto <nextMaskBit>;
resultTmp = resultTmp | (maskBit * (sourceTmp & 1));
sourceTmp = sourceTmp >> 1;
<nextMaskBit>
indexTmp = indexTmp << 1;
if (indexTmp != 0) goto <loop>;
Reg64 = resultTmp;
}
@endif
:PEXT Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32
{
indexTmp:4 = 0x80000000;
resultTmp:4 = 0;
<loop>
maskBit:4 = rm32 & indexTmp;
if (maskBit == 0) goto <nextMaskBit>;
resultTmp = (resultTmp << 1) | zext((maskBit & vexVVVV_r32) != 0);
<nextMaskBit>
indexTmp = indexTmp >> 1;
if (indexTmp != 0) goto <loop>;
build check_Reg32_dest;
Reg32 = resultTmp;
}
@ifdef IA64
:PEXT Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64
{
indexTmp:8 = 0x8000000000000000;
resultTmp:8 = 0;
<loop>
maskBit:8 = rm64 & indexTmp;
if (maskBit == 0) goto <nextMaskBit>;
resultTmp = (resultTmp << 1) | zext((maskBit & vexVVVV_r64) != 0);
<nextMaskBit>
indexTmp = indexTmp >> 1;
if (indexTmp != 0) goto <loop>;
Reg64 = resultTmp;
}
@endif
:RORX Reg32, rm32, imm8 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F3A) & $(VEX_W0); byte=0xf0; Reg32 ... & check_Reg32_dest ... & rm32; imm8
{
shiftTmp:1 = (imm8:1 & 0x1F);
Reg32 = (rm32 >> shiftTmp) | ( rm32 << (32 - shiftTmp));
build check_Reg32_dest;
}
@ifdef IA64
:RORX Reg64, rm64, imm8 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F3A) & $(VEX_W1); byte=0xf0; Reg64 ... & rm64; imm8
{
shiftTmp:1 = (imm8:1 & 0x3F);
Reg64 = (rm64 >> shiftTmp) | ( rm64 << (64 - shiftTmp));
}
@endif
:SARX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32
{
Reg32 = rm32 s>> (vexVVVV_r32 & 0x0000001F);
build check_Reg32_dest;
}
@ifdef IA64
:SARX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64
{
Reg64 = rm64 s>> (vexVVVV_r64 & 0x000000000000003F);
}
@endif
:SHLX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32
{
Reg32 = rm32 << (vexVVVV_r32 & 0x0000001F);
build check_Reg32_dest;
}
@ifdef IA64
:SHLX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64
{
Reg64 = rm64 << (vexVVVV_r64 & 0x000000000000003F);
}
@endif
:SHRX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32
{
Reg32 = rm32 >> (vexVVVV_r32 & 0x0000001F);
build check_Reg32_dest;
}
@ifdef IA64
:SHRX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64
{
Reg64 = rm64 >> (vexVVVV_r64 & 0x000000000000003F);
}
@endif

84
src/icicle/data/Ghidra/Processors/x86/data/languages/cet.sinc Normal file
View File

@@ -0,0 +1,84 @@
#
# Instructions based on Intel Control-flow Enforcement Technology Preview
#
# Note: Shadow Stack semantics is not currently implemented correctly in these instructions
# nor in the instructions affected by CET
#
define pcodeop ShadowStackPush8B;
define pcodeop ShadowStackPush4B;
define pcodeop ShadowStackLoad8B;
define pcodeop ShadowStackLoad4B;
:INCSSPD r32 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0xae; reg_opcode=5 & r32 {
SSP = SSP + zext(4 * r32:1);
}
@ifdef IA64
:INCSSPQ r64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & $(REX_W) & byte=0x0f; byte=0xae; reg_opcode=5 & r64 {
SSP = SSP + zext(8 * r64:1);
}
@endif
:RDSSPD r32 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x1e; mod=3 & reg_opcode=1 & r32 {
r32 = SSP:4;
}
@ifdef IA64
:RDSSPQ r64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & $(REX_W) & byte=0x0f; byte=0x1e; mod=3 & reg_opcode=1 & r64 {
r64 = SSP;
}
@endif
:SAVEPREVSSP is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; byte=0xea {
tmp:8 = SSP;
SSP = SSP & ~0x7;
ShadowStackPush8B(tmp);
}
:RSTORSSP m64 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; ( mod != 0b11 & reg_opcode=5 ) ... & m64 {
tmp_SSP:8 = m64;
SSP = tmp_SSP & ~0x01;
}
define pcodeop writeToShadowStack;
define pcodeop writeToUserShadowStack;
:WRSSD rm32,Reg32 is vexMode=0 & byte=0x0f; byte=0x38; byte=0xf6; rm32 & Reg32 ... {
writeToShadowStack(rm32, Reg32);
}
@ifdef IA64
:WRSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf6; rm64 & Reg64 ... {
writeToShadowStack(rm64, Reg64);
}
@endif
:WRUSSD rm32,Reg32 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0xf5; rm32 & Reg32 ... {
writeToUserShadowStack(rm32, Reg32);
}
@ifdef IA64
:WRUSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf5; rm64 & Reg64 ... {
writeToUserShadowStack(rm64, Reg64);
}
@endif
define pcodeop markShadowStackBusy;
define pcodeop clearShadowStackBusy;
:SETSSBSY is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; byte=0xe8 {
SSP = markShadowStackBusy(IA32_PL0_SSP);
}
:CLRSSBSY m64 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0xae; reg_opcode=6 ... & m64 {
clearShadowStackBusy(m64);
SSP=0;
}
:ENDBR32 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x1e; byte=0xfb {}
@ifdef IA64
:ENDBR64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x1e; byte=0xfa {}
@endif

14
src/icicle/data/Ghidra/Processors/x86/data/languages/clwb.sinc Normal file
View File

@@ -0,0 +1,14 @@
define pcodeop clwb;
:CLWB m8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=6 ... {
clwb(m8);
}
@ifdef IA64
define pcodeop clflushopt;
:CLFLUSHOPT m8 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=7 ... {
clflushopt(m8);
}
@endif
# Note: PCOMMIT was deprecated prior to it ever being implemented in production processors.
# I never found the encoding for it. Therefore, no constructor.

800
src/icicle/data/Ghidra/Processors/x86/data/languages/fma.sinc Normal file
View File

@@ -0,0 +1,800 @@
#
# x86 FMA instructions
#
# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101211
define pcodeop vfmadd132pd_fma ;
:VFMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101214
define pcodeop vfmadd213pd_fma ;
:VFMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101217
define pcodeop vfmadd231pd_fma ;
:VFMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101220
:VFMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x98; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101223
:VFMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA8; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101226
:VFMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB8; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101572
define pcodeop vfmadd132ps_fma ;
:VFMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101575
define pcodeop vfmadd213ps_fma ;
:VFMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101578
define pcodeop vfmadd231ps_fma ;
:VFMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101581
:VFMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x98; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101584
:VFMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA8; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101587
# WARNING: did not recognize VEX field 0 for "VFMADD231PS ymm1, ymm2, ymm3/m256"
:VFMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xB8; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101931
define pcodeop vfmadd132sd_fma ;
:VFMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101934
define pcodeop vfmadd213sd_fma ;
:VFMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101937
define pcodeop vfmadd231sd_fma ;
:VFMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102099
define pcodeop vfmadd132ss_fma ;
:VFMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102102
define pcodeop vfmadd213ss_fma ;
:VFMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102105
define pcodeop vfmadd231ss_fma ;
:VFMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102272
define pcodeop vfmaddsub132pd_fma ;
:VFMADDSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmaddsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102275
define pcodeop vfmaddsub213pd_fma ;
:VFMADDSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmaddsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102278
define pcodeop vfmaddsub231pd_fma ;
:VFMADDSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmaddsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102281
:VFMADDSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x96; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmaddsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102284
:VFMADDSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA6; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmaddsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102287
:VFMADDSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB6; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmaddsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102711
define pcodeop vfmaddsub132ps_fma ;
:VFMADDSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmaddsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102714
define pcodeop vfmaddsub213ps_fma ;
:VFMADDSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmaddsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102717
define pcodeop vfmaddsub231ps_fma ;
:VFMADDSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmaddsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102720
:VFMADDSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x96; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmaddsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102723
:VFMADDSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA6; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmaddsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102726
:VFMADDSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB6; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmaddsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103141
define pcodeop vfmsubadd132pd_fma ;
:VFMSUBADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsubadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103144
define pcodeop vfmsubadd213pd_fma ;
:VFMSUBADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsubadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103147
define pcodeop vfmsubadd231pd_fma ;
:VFMSUBADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsubadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103150
:VFMSUBADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsubadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103153
:VFMSUBADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsubadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103156
:VFMSUBADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsubadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103581
define pcodeop vfmsubadd132ps_fma ;
:VFMSUBADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsubadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103584
define pcodeop vfmsubadd213ps_fma ;
:VFMSUBADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsubadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103587
define pcodeop vfmsubadd231ps_fma ;
:VFMSUBADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsubadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103590
:VFMSUBADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsubadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103593
:VFMSUBADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsubadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103596
:VFMSUBADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsubadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104019
define pcodeop vfmsub132pd_fma ;
:VFMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104022
define pcodeop vfmsub213pd_fma ;
:VFMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104025
define pcodeop vfmsub231pd_fma ;
:VFMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104028
:VFMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9A; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104031
:VFMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAA; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104034
:VFMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBA; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104379
define pcodeop vfmsub132ps_fma ;
:VFMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104382
define pcodeop vfmsub213ps_fma ;
:VFMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104385
define pcodeop vfmsub231ps_fma ;
:VFMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104388
:VFMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9A; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104391
:VFMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAA; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104394
# WARNING: did not recognize VEX field 0 for "VFMSUB231PS ymm1, ymm2, ymm3/m256"
:VFMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBA; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104738
define pcodeop vfmsub132sd_fma ;
:VFMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104741
define pcodeop vfmsub213sd_fma ;
:VFMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104744
define pcodeop vfmsub231sd_fma ;
:VFMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104913
define pcodeop vfmsub132ss_fma ;
:VFMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104916
define pcodeop vfmsub213ss_fma ;
:VFMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104919
define pcodeop vfmsub231ss_fma ;
:VFMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105088
define pcodeop vfnmadd132pd_fma ;
:VFNMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105091
define pcodeop vfnmadd213pd_fma ;
:VFNMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105094
define pcodeop vfnmadd231pd_fma ;
:VFNMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105097
:VFNMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9C; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105100
:VFNMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAC; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105103
:VFNMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBC; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105447
define pcodeop vfnmadd132ps_fma ;
:VFNMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105450
define pcodeop vfnmadd213ps_fma ;
:VFNMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105453
define pcodeop vfnmadd231ps_fma ;
:VFNMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105456
:VFNMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9C; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105459
:VFNMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAC; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105462
# WARNING: did not recognize VEX field 0 for "VFNMADD231PS ymm1, ymm2, ymm3/m256"
:VFNMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBC; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105794
define pcodeop vfnmadd132sd_fma ;
:VFNMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfnmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105797
define pcodeop vfnmadd213sd_fma ;
:VFNMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfnmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105800
define pcodeop vfnmadd231sd_fma ;
:VFNMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfnmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105966
define pcodeop vfnmadd132ss_fma ;
:VFNMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfnmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105969
define pcodeop vfnmadd213ss_fma ;
:VFNMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfnmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105972
define pcodeop vfnmadd231ss_fma ;
:VFNMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfnmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106138
define pcodeop vfnmsub132pd_fma ;
:VFNMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106141
define pcodeop vfnmsub213pd_fma ;
:VFNMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106144
define pcodeop vfnmsub231pd_fma ;
:VFNMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106147
:VFNMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9E; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106150
:VFNMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAE; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106153
:VFNMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBE; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106487
define pcodeop vfnmsub132ps_fma ;
:VFNMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106490
define pcodeop vfnmsub213ps_fma ;
:VFNMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106493
define pcodeop vfnmsub231ps_fma ;
:VFNMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vfnmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106496
:VFNMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9E; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106499
:VFNMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAE; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106502
# WARNING: did not recognize VEX field 0 for "VFNMSUB231PS ymm1, ymm2, ymm3/m256"
:VFNMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBE; YmmReg1 ... & YmmReg2_m256
{
YmmReg1 = vfnmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 );
# TODO ZmmReg1 = zext(YmmReg1)
}
# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106832
define pcodeop vfnmsub132sd_fma ;
:VFNMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfnmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106835
define pcodeop vfnmsub213sd_fma ;
:VFNMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfnmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106838
define pcodeop vfnmsub231sd_fma ;
:VFNMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & YmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vfnmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107004
define pcodeop vfnmsub132ss_fma ;
:VFNMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfnmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107007
define pcodeop vfnmsub213ss_fma ;
:VFNMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfnmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}
# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107010
define pcodeop vfnmsub231ss_fma ;
:VFNMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & YmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vfnmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 );
YmmReg1 = zext(tmp);
# TODO ZmmReg1 = zext(XmmReg1)
}

9100
src/icicle/data/Ghidra/Processors/x86/data/languages/ia.sinc Normal file
View File

File diff suppressed because it is too large Load Diff

1380
src/icicle/data/Ghidra/Processors/x86/data/languages/lockable.sinc Normal file
View File

File diff suppressed because it is too large Load Diff

32
src/icicle/data/Ghidra/Processors/x86/data/languages/lzcnt.sinc Normal file
View File

@@ -0,0 +1,32 @@
macro lzcntflags(input, output) {
ZF = (output == 0);
CF = (input == 0);
# OF, SF, PF, AF are undefined
}
####
#### LZCNT instructions
####
:LZCNT Reg16, rm16 is vexMode=0 & opsize=0 & $(PRE_66) & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg16 ... & rm16 {
Reg16 = lzcount(rm16);
lzcntflags(rm16, Reg16);
}
:LZCNT Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg32 ... & check_Reg32_dest ... & rm32 {
Reg32 = lzcount(rm32);
lzcntflags(rm32, Reg32);
build check_Reg32_dest;
}
@ifdef IA64
:LZCNT Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xBD; Reg64 ... & rm64 {
Reg64 = lzcount(rm64);
lzcntflags(rm64, Reg64);
}
@endif

3
src/icicle/data/Ghidra/Processors/x86/data/languages/macros.sinc Normal file
View File

@@ -0,0 +1,3 @@
macro conditionalAssign(dest, cond, trueVal, falseVal) {
dest = zext(cond) * trueVal | zext(!cond) * falseVal;
}

234
src/icicle/data/Ghidra/Processors/x86/data/languages/mpx.sinc Normal file
View File

@@ -0,0 +1,234 @@
define pcodeop br_exception;
# BNDMK needs the base address register only
# - if no base register, needs 0
@ifdef IA64
bndmk_addr64: [Rmr64] is mod=0 & Rmr64 { export Rmr64; }
bndmk_addr64: [Rmr64 + simm8_64] is mod=1 & Rmr64; simm8_64 { export Rmr64; }
bndmk_addr64: [simm32_64 + Rmr64] is mod=2 & Rmr64; simm32_64 { export Rmr64; }
bndmk_addr64: [Rmr64] is mod=1 & r_m!=4 & Rmr64; simm8=0 { export Rmr64; }
bndmk_addr64: [Rmr64] is mod=2 & r_m!=4 & Rmr64; simm32=0 { export Rmr64; }
#invalid bndmk_addr64: [riprel] is mod=0 & r_m=5; simm32 [ riprel=inst_next+simm32; ] { export *[const]:8 riprel; }
bndmk_addr64: [Base64 + Index64*ss] is mod=0 & r_m=4; Index64 & Base64 & ss { export Base64; }
bndmk_addr64: [Base64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & Base64 { export Base64; }
bndmk_addr64: [simm32_64 + Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; simm32_64 { tmp:8 = 0; export tmp; }
bndmk_addr64: [Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; imm32=0 { tmp:8 = 0; export tmp; }
bndmk_addr64: [simm32_64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & base64=5; simm32_64 { tmp:8 = 0; export tmp; }
bndmk_addr64: [Base64 + Index64*ss + simm8_64] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8_64 { export Base64; }
bndmk_addr64: [Base64 + Index64*ss] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8=0 { export Base64; }
bndmk_addr64: [Base64 + simm8_64] is mod=1 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm8_64 { export Base64; }
bndmk_addr64: [simm32_64 + Base64 + Index64*ss] is mod=2 & r_m=4; Index64 & Base64 & ss; simm32_64 { export Base64; }
bndmk_addr64: [simm32_64 + Base64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm32_64 { export Base64; }
bndmk_addr64: [Base64 + Index64*ss] is mod=2 & r_m=4; Index64 & Base64 & ss; imm32=0 { export Base64; }
bndmk_addr64: [Base64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; imm32=0 { export Base64; }
@endif
bndmk_addr32: [Rmr32] is mod=0 & Rmr32 { export Rmr32; }
bndmk_addr32: [Rmr32 + simm8_32] is mod=1 & Rmr32; simm8_32 { export Rmr32; }
bndmk_addr32: [Rmr32] is mod=1 & r_m!=4 & Rmr32; simm8=0 { export Rmr32; }
bndmk_addr32: [imm32 + Rmr32] is mod=2 & Rmr32; imm32 { export Rmr32; }
bndmk_addr32: [Rmr32] is mod=2 & r_m!=4 & Rmr32; imm32=0 { export Rmr32; }
bndmk_addr32: [imm32] is mod=0 & r_m=5; imm32 { tmp:4 = 0; export tmp; }
bndmk_addr32: [Base + Index*ss] is mod=0 & r_m=4; Index & Base & ss { export Base; }
bndmk_addr32: [Base] is mod=0 & r_m=4; index=4 & Base { export Base; }
bndmk_addr32: [imm32 + Index*ss] is mod=0 & r_m=4; Index & base=5 & ss; imm32 { tmp:4 = 0; export tmp; }
bndmk_addr32: [imm32] is mod=0 & r_m=4; index=4 & base=5; imm32 { tmp:4 = 0; export tmp; }
bndmk_addr32: [Base + Index*ss + simm8_32] is mod=1 & r_m=4; Index & Base & ss; simm8_32 { export Base; }
bndmk_addr32: [Base + simm8_32] is mod=1 & r_m=4; index=4 & Base; simm8_32 { export Base; }
bndmk_addr32: [Base + Index*ss] is mod=1 & r_m=4; Index & Base & ss; simm8=0 { export Base; }
bndmk_addr32: [Base] is mod=1 & r_m=4; index=4 & Base; simm8=0 { export Base; }
bndmk_addr32: [imm32 + Base + Index*ss] is mod=2 & r_m=4; Index & Base & ss; imm32 { export Base; }
bndmk_addr32: [imm32 + Base] is mod=2 & r_m=4; index=4 & Base; imm32 { export Base; }
bndmk_addr32: [Base + Index*ss] is mod=2 & r_m=4; Index & Base & ss; imm32=0 { export Base; }
bndmk_addr32: [Base] is mod=2 & r_m=4; index=4 & Base; imm32=0 { export Base; }
@ifdef IA64
:BNDCL bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_lb & Rmr64 {
# if (reg < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(Rmr64 < bnd1_lb) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCL bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_lb) ... & Mem {
# if (LEA(mem) < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(Mem < bnd1_lb) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCU bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_ub & Rmr64 {
# if (reg > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(Rmr64 > ~bnd1_ub) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCU bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_ub) ... & Mem {
# if (LEA(mem) > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(Mem > ~bnd1_ub) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCN bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd1_ub & Rmr64 {
# if (reg > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(Rmr64 > bnd1_ub) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCN bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; (bnd1 & bnd1_ub) ... & Mem {
# if (LEA(mem) > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(Mem > bnd1_ub) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
#TODO: This probably cannot be fully modeled
:BNDLDX bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0x1A; bnd1 ... & Mem {
# BNDSTATUS = bndldx_status( Mem, BNDCFGS, BNDCFGU );
# bnd1 = bndldx( Mem, BNDCFGS, BNDCFGU );
# core implementation
bnd1 = *:16 Mem;
}
:BNDMK bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & ( bndmk_addr64 & Mem ) {
# BND.LB and BND.UB set from m64
bnd1_lb = bndmk_addr64;
bnd1_ub = Mem;
}
:BNDMOV bnd1, m128 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; bnd1 ... & m128 {
bnd1 = m128;
}
:BNDMOV bnd1, bnd2 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd2 {
bnd1 = bnd2;
}
:BNDMOV m128, bnd1 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; bnd1 ... & m128 {
m128 = bnd1;
}
:BNDMOV bnd2, bnd1 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd2 {
bnd2 = bnd1;
}
#TODO: This probably cannot be fully modeled
:BNDSTX Mem, bnd1 is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0x1B; bnd1 ... & Mem {
# BNDSTATUS = bndstx_status( bnd1, BNDCFGS, BNDCFGU );
# Mem = bndstx( bnd1, BNDCFGS, BNDCFGU );
# core implementation
*:16 Mem = bnd1;
}
@endif
:BNDCL bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_lb & Rmr32 {
# if (reg < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(zext(Rmr32) < bnd1_lb) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCL bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_lb) ... & Mem {
# if (LEA(mem) < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(zext(Mem) < bnd1_lb) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCU bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_ub & Rmr32 {
# if (reg > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(zext(Rmr32) > ~bnd1_ub) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCU bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_ub) ... & Mem {
# if (LEA(mem) > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(zext(Mem) > ~bnd1_ub) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCN bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd1_ub & Rmr32 {
# if (reg > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(zext(Rmr32) > bnd1_ub) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
:BNDCN bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; (bnd1 & bnd1_ub) ... & Mem {
# if (LEA(mem) > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION
if !(zext(Mem) > bnd1_ub) goto <done>;
BNDSTATUS = 0x01;
br_exception();
<done>
}
#TODO: This probably cannot be fully modeled
:BNDLDX bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0x1A; ( bnd1 & bnd1_lb & bnd1_ub ) ... & Mem {
# BNDSTATUS = bndldx_status( Mem, BNDCFGS, BNDCFGU );
# bnd1 = bndldx( Mem, BNDCFGS, BNDCFGU );
# core implementation
tmp:8 = *:8 Mem;
bnd1_lb = zext(tmp:4);
tmp2:4 = tmp(4);
bnd1_ub = zext(tmp2);
}
:BNDMK bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & ( bndmk_addr32 & Mem ) {
# BND.LB and BND.UB set from m32
bnd1_lb = zext(bndmk_addr32);
bnd1_ub = zext(Mem);
}
:BNDMOV bnd1, m64 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; ( bnd1 & bnd1_lb & bnd1_ub ) ... & m64 {
tmp:8 = m64;
bnd1_lb = zext(tmp:4);
tmp2:4 = tmp(4);
bnd1_ub = zext(tmp2);
}
:BNDMOV bnd1, bnd2 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd2 {
bnd1 = bnd2;
}
:BNDMOV m64, bnd1 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & m64 {
m64 = (zext(bnd1_ub:4) << 32) | zext(bnd1_lb:4);
}
:BNDMOV bnd2, bnd1 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd2 {
bnd2 = bnd1;
}
#TODO: This probably cannot be fully modeled
:BNDSTX Mem, bnd1 is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & Mem {
# BNDSTATUS = bndstx_status( bnd1, BNDCFGS, BNDCFGU );
# Mem = bndstx( bnd1, BNDCFGS, BNDCFGU );
# core implementation
*:8 Mem = (zext(bnd1_ub:4) << 32) | zext(bnd1_lb:4);
}

150
src/icicle/data/Ghidra/Processors/x86/data/languages/old/x86RealV1.lang Normal file
View File

@@ -0,0 +1,150 @@
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="little">
<description>
<id>x86:LE:16:Real Mode</id>
<processor>x86</processor>
</description>
<compiler name="default" id="default"/>
<spaces>
<segmented_space name="ram" default="yes" />
<space name="register" type="register" size="4" />
</spaces>
<registers>
<context_register name="contextreg" offset="0x2000" bitsize="32">
<field name="lockprefx" range="8,8" />
<field name="repprefx" range="7,7" />
<field name="repneprefx" range="6,6" />
<field name="sstype" range="5,5" />
<field name="segover" range="2,4" />
<field name="opsize" range="1,1" />
<field name="addrsize" range="0,0" />
</context_register>
<register name="EAX" offset="0x0" bitsize="32" />
<register name="ECX" offset="0x4" bitsize="32" />
<register name="EDX" offset="0x8" bitsize="32" />
<register name="EBX" offset="0xc" bitsize="32" />
<register name="ESP" offset="0x10" bitsize="32" />
<register name="EBP" offset="0x14" bitsize="32" />
<register name="ESI" offset="0x18" bitsize="32" />
<register name="EDI" offset="0x1c" bitsize="32" />
<register name="AX" offset="0x0" bitsize="16" />
<register name="CX" offset="0x4" bitsize="16" />
<register name="DX" offset="0x8" bitsize="16" />
<register name="BX" offset="0xc" bitsize="16" />
<register name="SP" offset="0x10" bitsize="16" />
<register name="BP" offset="0x14" bitsize="16" />
<register name="SI" offset="0x18" bitsize="16" />
<register name="DI" offset="0x1c" bitsize="16" />
<register name="AL" offset="0x0" bitsize="8" />
<register name="AH" offset="0x1" bitsize="8" />
<register name="CL" offset="0x4" bitsize="8" />
<register name="CH" offset="0x5" bitsize="8" />
<register name="DL" offset="0x8" bitsize="8" />
<register name="DH" offset="0x9" bitsize="8" />
<register name="BL" offset="0xc" bitsize="8" />
<register name="BH" offset="0xd" bitsize="8" />
<register name="ES" offset="0x100" bitsize="16" />
<register name="CS" offset="0x102" bitsize="16" />
<register name="SS" offset="0x104" bitsize="16" />
<register name="DS" offset="0x106" bitsize="16" />
<register name="FS" offset="0x108" bitsize="16" />
<register name="GS" offset="0x10a" bitsize="16" />
<register name="FS_OFFSET" offset="0x110" bitsize="32" />
<register name="CF" offset="0x200" bitsize="8" />
<register name="F1" offset="0x201" bitsize="8" />
<register name="PF" offset="0x202" bitsize="8" />
<register name="F3" offset="0x203" bitsize="8" />
<register name="AF" offset="0x204" bitsize="8" />
<register name="F5" offset="0x205" bitsize="8" />
<register name="ZF" offset="0x206" bitsize="8" />
<register name="SF" offset="0x207" bitsize="8" />
<register name="TF" offset="0x208" bitsize="8" />
<register name="IF" offset="0x209" bitsize="8" />
<register name="DF" offset="0x20a" bitsize="8" />
<register name="OF" offset="0x20b" bitsize="8" />
<register name="IOPL" offset="0x20c" bitsize="8" />
<register name="NT" offset="0x20d" bitsize="8" />
<register name="F15" offset="0x20e" bitsize="8" />
<register name="RF" offset="0x20f" bitsize="8" />
<register name="VM" offset="0x210" bitsize="8" />
<register name="AC" offset="0x211" bitsize="8" />
<register name="VIF" offset="0x212" bitsize="8" />
<register name="VIP" offset="0x213" bitsize="8" />
<register name="ID" offset="0x214" bitsize="8" />
<register name="eflags" offset="0x280" bitsize="32" />
<register name="EIP" offset="0x284" bitsize="32" />
<register name="flags" offset="0x280" bitsize="16" />
<register name="IP" offset="0x284" bitsize="16" />
<register name="DR0" offset="0x300" bitsize="32" />
<register name="DR1" offset="0x304" bitsize="32" />
<register name="DR2" offset="0x308" bitsize="32" />
<register name="DR3" offset="0x30c" bitsize="32" />
<register name="DR4" offset="0x310" bitsize="32" />
<register name="DR5" offset="0x314" bitsize="32" />
<register name="DR6" offset="0x318" bitsize="32" />
<register name="DR7" offset="0x31c" bitsize="32" />
<register name="CR0" offset="0x320" bitsize="32" />
<register name="CR2" offset="0x328" bitsize="32" />
<register name="CR3" offset="0x32c" bitsize="32" />
<register name="CR4" offset="0x330" bitsize="32" />
<register name="TR0" offset="0x400" bitsize="32" />
<register name="TR1" offset="0x404" bitsize="32" />
<register name="TR2" offset="0x408" bitsize="32" />
<register name="TR3" offset="0x40c" bitsize="32" />
<register name="TR4" offset="0x410" bitsize="32" />
<register name="TR5" offset="0x414" bitsize="32" />
<register name="TR6" offset="0x418" bitsize="32" />
<register name="TR7" offset="0x41c" bitsize="32" />
<register name="ST0" offset="0x1000" bitsize="80" />
<register name="ST1" offset="0x100a" bitsize="80" />
<register name="ST2" offset="0x1014" bitsize="80" />
<register name="ST3" offset="0x101e" bitsize="80" />
<register name="ST4" offset="0x1028" bitsize="80" />
<register name="ST5" offset="0x1032" bitsize="80" />
<register name="ST6" offset="0x103c" bitsize="80" />
<register name="ST7" offset="0x1046" bitsize="80" />
<register name="FPUControlWord" offset="0x1090" bitsize="16" />
<register name="FPUStatusWord" offset="0x1092" bitsize="16" />
<register name="FPUTagWord" offset="0x1094" bitsize="16" />
<register name="FPUDataPointer" offset="0x1096" bitsize="16" />
<register name="FPUInstructionPointer" offset="0x1098" bitsize="16" />
<register name="FPULastInstructionOpcode" offset="0x109a" bitsize="16" />
<register name="MM0" offset="0x1100" bitsize="64" />
<register name="MM1" offset="0x1108" bitsize="64" />
<register name="MM2" offset="0x1110" bitsize="64" />
<register name="MM3" offset="0x1118" bitsize="64" />
<register name="MM4" offset="0x1120" bitsize="64" />
<register name="MM5" offset="0x1128" bitsize="64" />
<register name="MM6" offset="0x1130" bitsize="64" />
<register name="MM7" offset="0x1138" bitsize="64" />
<register name="XMM0" offset="0x1200" bitsize="128" />
<register name="XMM1" offset="0x1210" bitsize="128" />
<register name="XMM2" offset="0x1220" bitsize="128" />
<register name="XMM3" offset="0x1230" bitsize="128" />
<register name="XMM4" offset="0x1240" bitsize="128" />
<register name="XMM5" offset="0x1250" bitsize="128" />
<register name="XMM6" offset="0x1260" bitsize="128" />
<register name="XMM7" offset="0x1270" bitsize="128" />
<register name="XMM8" offset="0x1280" bitsize="128" />
<register name="XMM9" offset="0x1290" bitsize="128" />
<register name="XMM10" offset="0x12a0" bitsize="128" />
<register name="XMM11" offset="0x12b0" bitsize="128" />
<register name="XMM12" offset="0x12c0" bitsize="128" />
<register name="XMM13" offset="0x12d0" bitsize="128" />
<register name="XMM14" offset="0x12e0" bitsize="128" />
<register name="XMM15" offset="0x12f0" bitsize="128" />
<register name="IDTR" offset="0x2200" bitsize="48" />
<register name="IDTR_Limit" offset="0x2200" bitsize="16" />
<register name="IDTR_Address" offset="0x2202" bitsize="32" />
<register name="GDTR" offset="0x2210" bitsize="48" />
<register name="GDTR_Limit" offset="0x2210" bitsize="16" />
<register name="GDTR_Address" offset="0x2212" bitsize="32" />
<register name="LDTR" offset="0x2220" bitsize="48" />
<register name="LDTR_Limit" offset="0x2220" bitsize="16" />
<register name="LDTR_Address" offset="0x2222" bitsize="32" />
<register name="TR" offset="0x2230" bitsize="48" />
<register name="TR_Limit" offset="0x2230" bitsize="16" />
<register name="TR_Address" offset="0x2232" bitsize="32" />
</registers>
</language>

7
src/icicle/data/Ghidra/Processors/x86/data/languages/old/x86RealV1.trans Normal file
View File

@@ -0,0 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">x86:LE:16:Real Mode</from_language>
<to_language version="2">x86:LE:16:Real Mode</to_language>
<map_compiler_spec from="default" to="default" />
</language_translation>

151
src/icicle/data/Ghidra/Processors/x86/data/languages/old/x86V1.lang Normal file
View File

@@ -0,0 +1,151 @@
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="little">
<description>
<id>x86:LE:32:default</id>
<processor>x86</processor>
</description>
<compiler name="Visual Studio" id="windows"/>
<compiler name="gcc" id="gcc"/>
<spaces>
<space name="ram" type="ram" size="4" default="yes" />
<space name="register" type="register" size="4" />
</spaces>
<registers>
<context_register name="contextreg" offset="0x2000" bitsize="32">
<field name="lockprefx" range="8,8" />
<field name="repprefx" range="7,7" />
<field name="repneprefx" range="6,6" />
<field name="sstype" range="5,5" />
<field name="segover" range="2,4" />
<field name="opsize" range="1,1" />
<field name="addrsize" range="0,0" />
</context_register>
<register name="EAX" offset="0x0" bitsize="32" />
<register name="ECX" offset="0x4" bitsize="32" />
<register name="EDX" offset="0x8" bitsize="32" />
<register name="EBX" offset="0xc" bitsize="32" />
<register name="ESP" offset="0x10" bitsize="32" />
<register name="EBP" offset="0x14" bitsize="32" />
<register name="ESI" offset="0x18" bitsize="32" />
<register name="EDI" offset="0x1c" bitsize="32" />
<register name="AX" offset="0x0" bitsize="16" />
<register name="CX" offset="0x4" bitsize="16" />
<register name="DX" offset="0x8" bitsize="16" />
<register name="BX" offset="0xc" bitsize="16" />
<register name="SP" offset="0x10" bitsize="16" />
<register name="BP" offset="0x14" bitsize="16" />
<register name="SI" offset="0x18" bitsize="16" />
<register name="DI" offset="0x1c" bitsize="16" />
<register name="AL" offset="0x0" bitsize="8" />
<register name="AH" offset="0x1" bitsize="8" />
<register name="CL" offset="0x4" bitsize="8" />
<register name="CH" offset="0x5" bitsize="8" />
<register name="DL" offset="0x8" bitsize="8" />
<register name="DH" offset="0x9" bitsize="8" />
<register name="BL" offset="0xc" bitsize="8" />
<register name="BH" offset="0xd" bitsize="8" />
<register name="ES" offset="0x100" bitsize="16" />
<register name="CS" offset="0x102" bitsize="16" />
<register name="SS" offset="0x104" bitsize="16" />
<register name="DS" offset="0x106" bitsize="16" />
<register name="FS" offset="0x108" bitsize="16" />
<register name="GS" offset="0x10a" bitsize="16" />
<register name="FS_OFFSET" offset="0x110" bitsize="32" />
<register name="CF" offset="0x200" bitsize="8" />
<register name="F1" offset="0x201" bitsize="8" />
<register name="PF" offset="0x202" bitsize="8" />
<register name="F3" offset="0x203" bitsize="8" />
<register name="AF" offset="0x204" bitsize="8" />
<register name="F5" offset="0x205" bitsize="8" />
<register name="ZF" offset="0x206" bitsize="8" />
<register name="SF" offset="0x207" bitsize="8" />
<register name="TF" offset="0x208" bitsize="8" />
<register name="IF" offset="0x209" bitsize="8" />
<register name="DF" offset="0x20a" bitsize="8" />
<register name="OF" offset="0x20b" bitsize="8" />
<register name="IOPL" offset="0x20c" bitsize="8" />
<register name="NT" offset="0x20d" bitsize="8" />
<register name="F15" offset="0x20e" bitsize="8" />
<register name="RF" offset="0x20f" bitsize="8" />
<register name="VM" offset="0x210" bitsize="8" />
<register name="AC" offset="0x211" bitsize="8" />
<register name="VIF" offset="0x212" bitsize="8" />
<register name="VIP" offset="0x213" bitsize="8" />
<register name="ID" offset="0x214" bitsize="8" />
<register name="eflags" offset="0x280" bitsize="32" />
<register name="EIP" offset="0x284" bitsize="32" />
<register name="flags" offset="0x280" bitsize="16" />
<register name="IP" offset="0x284" bitsize="16" />
<register name="DR0" offset="0x300" bitsize="32" />
<register name="DR1" offset="0x304" bitsize="32" />
<register name="DR2" offset="0x308" bitsize="32" />
<register name="DR3" offset="0x30c" bitsize="32" />
<register name="DR4" offset="0x310" bitsize="32" />
<register name="DR5" offset="0x314" bitsize="32" />
<register name="DR6" offset="0x318" bitsize="32" />
<register name="DR7" offset="0x31c" bitsize="32" />
<register name="CR0" offset="0x320" bitsize="32" />
<register name="CR2" offset="0x328" bitsize="32" />
<register name="CR3" offset="0x32c" bitsize="32" />
<register name="CR4" offset="0x330" bitsize="32" />
<register name="TR0" offset="0x400" bitsize="32" />
<register name="TR1" offset="0x404" bitsize="32" />
<register name="TR2" offset="0x408" bitsize="32" />
<register name="TR3" offset="0x40c" bitsize="32" />
<register name="TR4" offset="0x410" bitsize="32" />
<register name="TR5" offset="0x414" bitsize="32" />
<register name="TR6" offset="0x418" bitsize="32" />
<register name="TR7" offset="0x41c" bitsize="32" />
<register name="ST0" offset="0x1000" bitsize="80" />
<register name="ST1" offset="0x100a" bitsize="80" />
<register name="ST2" offset="0x1014" bitsize="80" />
<register name="ST3" offset="0x101e" bitsize="80" />
<register name="ST4" offset="0x1028" bitsize="80" />
<register name="ST5" offset="0x1032" bitsize="80" />
<register name="ST6" offset="0x103c" bitsize="80" />
<register name="ST7" offset="0x1046" bitsize="80" />
<register name="FPUControlWord" offset="0x1090" bitsize="16" />
<register name="FPUStatusWord" offset="0x1092" bitsize="16" />
<register name="FPUTagWord" offset="0x1094" bitsize="16" />
<register name="FPUDataPointer" offset="0x1096" bitsize="16" />
<register name="FPUInstructionPointer" offset="0x1098" bitsize="16" />
<register name="FPULastInstructionOpcode" offset="0x109a" bitsize="16" />
<register name="MM0" offset="0x1100" bitsize="64" />
<register name="MM1" offset="0x1108" bitsize="64" />
<register name="MM2" offset="0x1110" bitsize="64" />
<register name="MM3" offset="0x1118" bitsize="64" />
<register name="MM4" offset="0x1120" bitsize="64" />
<register name="MM5" offset="0x1128" bitsize="64" />
<register name="MM6" offset="0x1130" bitsize="64" />
<register name="MM7" offset="0x1138" bitsize="64" />
<register name="XMM0" offset="0x1200" bitsize="128" />
<register name="XMM1" offset="0x1210" bitsize="128" />
<register name="XMM2" offset="0x1220" bitsize="128" />
<register name="XMM3" offset="0x1230" bitsize="128" />
<register name="XMM4" offset="0x1240" bitsize="128" />
<register name="XMM5" offset="0x1250" bitsize="128" />
<register name="XMM6" offset="0x1260" bitsize="128" />
<register name="XMM7" offset="0x1270" bitsize="128" />
<register name="XMM8" offset="0x1280" bitsize="128" />
<register name="XMM9" offset="0x1290" bitsize="128" />
<register name="XMM10" offset="0x12a0" bitsize="128" />
<register name="XMM11" offset="0x12b0" bitsize="128" />
<register name="XMM12" offset="0x12c0" bitsize="128" />
<register name="XMM13" offset="0x12d0" bitsize="128" />
<register name="XMM14" offset="0x12e0" bitsize="128" />
<register name="XMM15" offset="0x12f0" bitsize="128" />
<register name="IDTR" offset="0x2200" bitsize="48" />
<register name="IDTR_Limit" offset="0x2200" bitsize="16" />
<register name="IDTR_Address" offset="0x2202" bitsize="32" />
<register name="GDTR" offset="0x2210" bitsize="48" />
<register name="GDTR_Limit" offset="0x2210" bitsize="16" />
<register name="GDTR_Address" offset="0x2212" bitsize="32" />
<register name="LDTR" offset="0x2220" bitsize="48" />
<register name="LDTR_Limit" offset="0x2220" bitsize="16" />
<register name="LDTR_Address" offset="0x2222" bitsize="32" />
<register name="TR" offset="0x2230" bitsize="48" />
<register name="TR_Limit" offset="0x2230" bitsize="16" />
<register name="TR_Address" offset="0x2232" bitsize="32" />
</registers>
</language>

8
src/icicle/data/Ghidra/Processors/x86/data/languages/old/x86V1.trans Normal file
View File

@@ -0,0 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">x86:LE:32:default</from_language>
<to_language version="2">x86:LE:32:default</to_language>
<map_compiler_spec from="windows" to="windows" />
<map_compiler_spec from="gcc" to="gcc" />
</language_translation>

221
src/icicle/data/Ghidra/Processors/x86/data/languages/old/x86_64bit_v1.lang Normal file
View File

@@ -0,0 +1,221 @@
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="little">
<description>
<id>x64:LE:64:default</id>
<processor>x64</processor>
</description>
<compiler name="Visual Studio" id="windows"/>
<compiler name="gcc" id="gcc"/>
<spaces>
<space name="ram" type="ram" size="8" default="yes" />
<space name="register" type="register" size="4" />
</spaces>
<registers>
<context_register name="contextreg" offset="0x2000" bitsize="32">
<field name="rexprefix" range="15,15" />
<field name="rexBprefix" range="14,14" />
<field name="rexXprefix" range="13,13" />
<field name="rexRprefix" range="12,12" />
<field name="rexWprefix" range="11,11" />
<field name="lockprefx" range="10,10" />
<field name="repprefx" range="9,9" />
<field name="repneprefx" range="8,8" />
<field name="sstype" range="7,7" />
<field name="segover" range="4,6" />
<field name="opsize" range="2,3" />
<field name="addrsize" range="0,1" />
<field name="bit64" range="0,0" />
</context_register>
<register name="RAX" offset="0x0" bitsize="64" />
<register name="RCX" offset="0x8" bitsize="64" />
<register name="RDX" offset="0x10" bitsize="64" />
<register name="RBX" offset="0x18" bitsize="64" />
<register name="RSP" offset="0x20" bitsize="64" />
<register name="RBP" offset="0x28" bitsize="64" />
<register name="RSI" offset="0x30" bitsize="64" />
<register name="RDI" offset="0x38" bitsize="64" />
<register name="EAX" offset="0x0" bitsize="32" />
<register name="ECX" offset="0x8" bitsize="32" />
<register name="EDX" offset="0x10" bitsize="32" />
<register name="EBX" offset="0x18" bitsize="32" />
<register name="ESP" offset="0x20" bitsize="32" />
<register name="EBP" offset="0x28" bitsize="32" />
<register name="ESI" offset="0x30" bitsize="32" />
<register name="EDI" offset="0x38" bitsize="32" />
<register name="AX" offset="0x0" bitsize="16" />
<register name="CX" offset="0x8" bitsize="16" />
<register name="DX" offset="0x10" bitsize="16" />
<register name="BX" offset="0x18" bitsize="16" />
<register name="SP" offset="0x20" bitsize="16" />
<register name="BP" offset="0x28" bitsize="16" />
<register name="SI" offset="0x30" bitsize="16" />
<register name="DI" offset="0x38" bitsize="16" />
<register name="AL" offset="0x0" bitsize="8" />
<register name="AH" offset="0x1" bitsize="8" />
<register name="CL" offset="0x8" bitsize="8" />
<register name="CH" offset="0x9" bitsize="8" />
<register name="DL" offset="0x10" bitsize="8" />
<register name="DH" offset="0x11" bitsize="8" />
<register name="BL" offset="0x18" bitsize="8" />
<register name="BH" offset="0x19" bitsize="8" />
<register name="SPL" offset="0x20" bitsize="8" />
<register name="BPL" offset="0x28" bitsize="8" />
<register name="SIL" offset="0x30" bitsize="8" />
<register name="DIL" offset="0x38" bitsize="8" />
<register name="R8" offset="0x80" bitsize="64" />
<register name="R9" offset="0x88" bitsize="64" />
<register name="R10" offset="0x90" bitsize="64" />
<register name="R11" offset="0x98" bitsize="64" />
<register name="R12" offset="0xa0" bitsize="64" />
<register name="R13" offset="0xa8" bitsize="64" />
<register name="R14" offset="0xb0" bitsize="64" />
<register name="R15" offset="0xb8" bitsize="64" />
<register name="R8D" offset="0x80" bitsize="32" />
<register name="R9D" offset="0x88" bitsize="32" />
<register name="R10D" offset="0x90" bitsize="32" />
<register name="R11D" offset="0x98" bitsize="32" />
<register name="R12D" offset="0xa0" bitsize="32" />
<register name="R13D" offset="0xa8" bitsize="32" />
<register name="R14D" offset="0xb0" bitsize="32" />
<register name="R15D" offset="0xb8" bitsize="32" />
<register name="R8W" offset="0x80" bitsize="16" />
<register name="R9W" offset="0x88" bitsize="16" />
<register name="R10W" offset="0x90" bitsize="16" />
<register name="R11W" offset="0x98" bitsize="16" />
<register name="R12W" offset="0xa0" bitsize="16" />
<register name="R13W" offset="0xa8" bitsize="16" />
<register name="R14W" offset="0xb0" bitsize="16" />
<register name="R15W" offset="0xb8" bitsize="16" />
<register name="R8B" offset="0x80" bitsize="8" />
<register name="R9B" offset="0x88" bitsize="8" />
<register name="R10B" offset="0x90" bitsize="8" />
<register name="R11B" offset="0x98" bitsize="8" />
<register name="R12B" offset="0xa0" bitsize="8" />
<register name="R13B" offset="0xa8" bitsize="8" />
<register name="R14B" offset="0xb0" bitsize="8" />
<register name="R15B" offset="0xb8" bitsize="8" />
<register name="ES" offset="0x100" bitsize="16" />
<register name="CS" offset="0x102" bitsize="16" />
<register name="SS" offset="0x104" bitsize="16" />
<register name="DS" offset="0x106" bitsize="16" />
<register name="FS" offset="0x108" bitsize="16" />
<register name="GS" offset="0x10a" bitsize="16" />
<register name="FS_OFFSET" offset="0x110" bitsize="32" />
<register name="CF" offset="0x200" bitsize="8" />
<register name="F1" offset="0x201" bitsize="8" />
<register name="PF" offset="0x202" bitsize="8" />
<register name="F3" offset="0x203" bitsize="8" />
<register name="AF" offset="0x204" bitsize="8" />
<register name="F5" offset="0x205" bitsize="8" />
<register name="ZF" offset="0x206" bitsize="8" />
<register name="SF" offset="0x207" bitsize="8" />
<register name="TF" offset="0x208" bitsize="8" />
<register name="IF" offset="0x209" bitsize="8" />
<register name="DF" offset="0x20a" bitsize="8" />
<register name="OF" offset="0x20b" bitsize="8" />
<register name="IOPL" offset="0x20c" bitsize="8" />
<register name="NT" offset="0x20d" bitsize="8" />
<register name="F15" offset="0x20e" bitsize="8" />
<register name="RF" offset="0x20f" bitsize="8" />
<register name="VM" offset="0x210" bitsize="8" />
<register name="AC" offset="0x211" bitsize="8" />
<register name="VIF" offset="0x212" bitsize="8" />
<register name="VIP" offset="0x213" bitsize="8" />
<register name="ID" offset="0x214" bitsize="8" />
<register name="rflags" offset="0x280" bitsize="64" />
<register name="RIP" offset="0x288" bitsize="64" />
<register name="eflags" offset="0x280" bitsize="32" />
<register name="EIP" offset="0x288" bitsize="32" />
<register name="flags" offset="0x280" bitsize="16" />
<register name="IP" offset="0x288" bitsize="16" />
<register name="DR0" offset="0x300" bitsize="64" />
<register name="DR1" offset="0x308" bitsize="64" />
<register name="DR2" offset="0x310" bitsize="64" />
<register name="DR3" offset="0x318" bitsize="64" />
<register name="DR4" offset="0x320" bitsize="64" />
<register name="DR5" offset="0x328" bitsize="64" />
<register name="DR6" offset="0x330" bitsize="64" />
<register name="DR7" offset="0x338" bitsize="64" />
<register name="DR8" offset="0x340" bitsize="64" />
<register name="DR9" offset="0x348" bitsize="64" />
<register name="DR10" offset="0x350" bitsize="64" />
<register name="DR11" offset="0x358" bitsize="64" />
<register name="DR12" offset="0x360" bitsize="64" />
<register name="DR13" offset="0x368" bitsize="64" />
<register name="DR14" offset="0x370" bitsize="64" />
<register name="DR15" offset="0x378" bitsize="64" />
<register name="CR0" offset="0x380" bitsize="64" />
<register name="CR1" offset="0x388" bitsize="64" />
<register name="CR2" offset="0x390" bitsize="64" />
<register name="CR3" offset="0x398" bitsize="64" />
<register name="CR4" offset="0x3a0" bitsize="64" />
<register name="CR5" offset="0x3a8" bitsize="64" />
<register name="CR6" offset="0x3b0" bitsize="64" />
<register name="CR7" offset="0x3b8" bitsize="64" />
<register name="CR8" offset="0x3c0" bitsize="64" />
<register name="CR9" offset="0x3c8" bitsize="64" />
<register name="CR10" offset="0x3d0" bitsize="64" />
<register name="CR11" offset="0x3d8" bitsize="64" />
<register name="CR12" offset="0x3e0" bitsize="64" />
<register name="CR13" offset="0x3e8" bitsize="64" />
<register name="CR14" offset="0x3f0" bitsize="64" />
<register name="CR15" offset="0x3f8" bitsize="64" />
<register name="ST0" offset="0x1000" bitsize="80" />
<register name="ST1" offset="0x100a" bitsize="80" />
<register name="ST2" offset="0x1014" bitsize="80" />
<register name="ST3" offset="0x101e" bitsize="80" />
<register name="ST4" offset="0x1028" bitsize="80" />
<register name="ST5" offset="0x1032" bitsize="80" />
<register name="ST6" offset="0x103c" bitsize="80" />
<register name="ST7" offset="0x1046" bitsize="80" />
<register name="C0" offset="0x1080" bitsize="8" />
<register name="C1" offset="0x1081" bitsize="8" />
<register name="C2" offset="0x1082" bitsize="8" />
<register name="C3" offset="0x1083" bitsize="8" />
<register name="FPUControlWord" offset="0x1090" bitsize="16" />
<register name="FPUStatusWord" offset="0x1092" bitsize="16" />
<register name="FPUTagWord" offset="0x1094" bitsize="16" />
<register name="FPUDataPointer" offset="0x1096" bitsize="16" />
<register name="FPUInstructionPointer" offset="0x1098" bitsize="16" />
<register name="FPULastInstructionOpcode" offset="0x109a" bitsize="16" />
<register name="MM0" offset="0x1100" bitsize="64" />
<register name="MM1" offset="0x1108" bitsize="64" />
<register name="MM2" offset="0x1110" bitsize="64" />
<register name="MM3" offset="0x1118" bitsize="64" />
<register name="MM4" offset="0x1120" bitsize="64" />
<register name="MM5" offset="0x1128" bitsize="64" />
<register name="MM6" offset="0x1130" bitsize="64" />
<register name="MM7" offset="0x1138" bitsize="64" />
<register name="XMM0" offset="0x1200" bitsize="128" />
<register name="XMM1" offset="0x1210" bitsize="128" />
<register name="XMM2" offset="0x1220" bitsize="128" />
<register name="XMM3" offset="0x1230" bitsize="128" />
<register name="XMM4" offset="0x1240" bitsize="128" />
<register name="XMM5" offset="0x1250" bitsize="128" />
<register name="XMM6" offset="0x1260" bitsize="128" />
<register name="XMM7" offset="0x1270" bitsize="128" />
<register name="XMM8" offset="0x1280" bitsize="128" />
<register name="XMM9" offset="0x1290" bitsize="128" />
<register name="XMM10" offset="0x12a0" bitsize="128" />
<register name="XMM11" offset="0x12b0" bitsize="128" />
<register name="XMM12" offset="0x12c0" bitsize="128" />
<register name="XMM13" offset="0x12d0" bitsize="128" />
<register name="XMM14" offset="0x12e0" bitsize="128" />
<register name="XMM15" offset="0x12f0" bitsize="128" />
<register name="IDTR_Limit" offset="0x2200" bitsize="32" />
<register name="IDTR" offset="0x2200" bitsize="96" />
<register name="IDTR_Address" offset="0x2204" bitsize="64" />
<register name="GDTR_Limit" offset="0x2220" bitsize="32" />
<register name="GDTR" offset="0x2220" bitsize="96" />
<register name="GDTR_Address" offset="0x2224" bitsize="64" />
<register name="LDTR_Limit" offset="0x2240" bitsize="32" />
<register name="LDTR" offset="0x2240" bitsize="112" />
<register name="LDTR_Address" offset="0x2244" bitsize="64" />
<register name="LDTR_Attributes" offset="0x2248" bitsize="16" />
<register name="TR_Limit" offset="0x2260" bitsize="32" />
<register name="TR" offset="0x2260" bitsize="112" />
<register name="TR_Address" offset="0x2264" bitsize="64" />
<register name="TR_Attributes" offset="0x2268" bitsize="16" />
</registers>
</language>

8
src/icicle/data/Ghidra/Processors/x86/data/languages/old/x86_64bit_v1.trans Normal file
View File

@@ -0,0 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">x64:LE:64:default</from_language>
<to_language version="2">x86:LE:64:default</to_language>
<map_compiler_spec from="windows" to="windows" />
<map_compiler_spec from="gcc" to="gcc" />
</language_translation>

150
src/icicle/data/Ghidra/Processors/x86/data/languages/old/x86smmV1.lang Normal file
View File

@@ -0,0 +1,150 @@
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="little">
<description>
<id>x86:LE:32:System Management Mode</id>
<processor>x86</processor>
</description>
<compiler name="default" id="default"/>
<spaces>
<space name="ram" type="ram" size="4" default="yes" />
<space name="register" type="register" size="4" />
</spaces>
<registers>
<context_register name="contextreg" offset="0x2000" bitsize="32">
<field name="lockprefx" range="8,8" />
<field name="repprefx" range="7,7" />
<field name="repneprefx" range="6,6" />
<field name="sstype" range="5,5" />
<field name="segover" range="2,4" />
<field name="opsize" range="1,1" />
<field name="addrsize" range="0,0" />
</context_register>
<register name="EAX" offset="0x0" bitsize="32" />
<register name="ECX" offset="0x4" bitsize="32" />
<register name="EDX" offset="0x8" bitsize="32" />
<register name="EBX" offset="0xc" bitsize="32" />
<register name="ESP" offset="0x10" bitsize="32" />
<register name="EBP" offset="0x14" bitsize="32" />
<register name="ESI" offset="0x18" bitsize="32" />
<register name="EDI" offset="0x1c" bitsize="32" />
<register name="AX" offset="0x0" bitsize="16" />
<register name="CX" offset="0x4" bitsize="16" />
<register name="DX" offset="0x8" bitsize="16" />
<register name="BX" offset="0xc" bitsize="16" />
<register name="SP" offset="0x10" bitsize="16" />
<register name="BP" offset="0x14" bitsize="16" />
<register name="SI" offset="0x18" bitsize="16" />
<register name="DI" offset="0x1c" bitsize="16" />
<register name="AL" offset="0x0" bitsize="8" />
<register name="AH" offset="0x1" bitsize="8" />
<register name="CL" offset="0x4" bitsize="8" />
<register name="CH" offset="0x5" bitsize="8" />
<register name="DL" offset="0x8" bitsize="8" />
<register name="DH" offset="0x9" bitsize="8" />
<register name="BL" offset="0xc" bitsize="8" />
<register name="BH" offset="0xd" bitsize="8" />
<register name="ES" offset="0x100" bitsize="16" />
<register name="CS" offset="0x102" bitsize="16" />
<register name="SS" offset="0x104" bitsize="16" />
<register name="DS" offset="0x106" bitsize="16" />
<register name="FS" offset="0x108" bitsize="16" />
<register name="GS" offset="0x10a" bitsize="16" />
<register name="FS_OFFSET" offset="0x110" bitsize="32" />
<register name="CF" offset="0x200" bitsize="8" />
<register name="F1" offset="0x201" bitsize="8" />
<register name="PF" offset="0x202" bitsize="8" />
<register name="F3" offset="0x203" bitsize="8" />
<register name="AF" offset="0x204" bitsize="8" />
<register name="F5" offset="0x205" bitsize="8" />
<register name="ZF" offset="0x206" bitsize="8" />
<register name="SF" offset="0x207" bitsize="8" />
<register name="TF" offset="0x208" bitsize="8" />
<register name="IF" offset="0x209" bitsize="8" />
<register name="DF" offset="0x20a" bitsize="8" />
<register name="OF" offset="0x20b" bitsize="8" />
<register name="IOPL" offset="0x20c" bitsize="8" />
<register name="NT" offset="0x20d" bitsize="8" />
<register name="F15" offset="0x20e" bitsize="8" />
<register name="RF" offset="0x20f" bitsize="8" />
<register name="VM" offset="0x210" bitsize="8" />
<register name="AC" offset="0x211" bitsize="8" />
<register name="VIF" offset="0x212" bitsize="8" />
<register name="VIP" offset="0x213" bitsize="8" />
<register name="ID" offset="0x214" bitsize="8" />
<register name="eflags" offset="0x280" bitsize="32" />
<register name="EIP" offset="0x284" bitsize="32" />
<register name="flags" offset="0x280" bitsize="16" />
<register name="IP" offset="0x284" bitsize="16" />
<register name="DR0" offset="0x300" bitsize="32" />
<register name="DR1" offset="0x304" bitsize="32" />
<register name="DR2" offset="0x308" bitsize="32" />
<register name="DR3" offset="0x30c" bitsize="32" />
<register name="DR4" offset="0x310" bitsize="32" />
<register name="DR5" offset="0x314" bitsize="32" />
<register name="DR6" offset="0x318" bitsize="32" />
<register name="DR7" offset="0x31c" bitsize="32" />
<register name="CR0" offset="0x320" bitsize="32" />
<register name="CR2" offset="0x328" bitsize="32" />
<register name="CR3" offset="0x32c" bitsize="32" />
<register name="CR4" offset="0x330" bitsize="32" />
<register name="TR0" offset="0x400" bitsize="32" />
<register name="TR1" offset="0x404" bitsize="32" />
<register name="TR2" offset="0x408" bitsize="32" />
<register name="TR3" offset="0x40c" bitsize="32" />
<register name="TR4" offset="0x410" bitsize="32" />
<register name="TR5" offset="0x414" bitsize="32" />
<register name="TR6" offset="0x418" bitsize="32" />
<register name="TR7" offset="0x41c" bitsize="32" />
<register name="ST0" offset="0x1000" bitsize="80" />
<register name="ST1" offset="0x100a" bitsize="80" />
<register name="ST2" offset="0x1014" bitsize="80" />
<register name="ST3" offset="0x101e" bitsize="80" />
<register name="ST4" offset="0x1028" bitsize="80" />
<register name="ST5" offset="0x1032" bitsize="80" />
<register name="ST6" offset="0x103c" bitsize="80" />
<register name="ST7" offset="0x1046" bitsize="80" />
<register name="FPUControlWord" offset="0x1090" bitsize="16" />
<register name="FPUStatusWord" offset="0x1092" bitsize="16" />
<register name="FPUTagWord" offset="0x1094" bitsize="16" />
<register name="FPUDataPointer" offset="0x1096" bitsize="16" />
<register name="FPUInstructionPointer" offset="0x1098" bitsize="16" />
<register name="FPULastInstructionOpcode" offset="0x109a" bitsize="16" />
<register name="MM0" offset="0x1100" bitsize="64" />
<register name="MM1" offset="0x1108" bitsize="64" />
<register name="MM2" offset="0x1110" bitsize="64" />
<register name="MM3" offset="0x1118" bitsize="64" />
<register name="MM4" offset="0x1120" bitsize="64" />
<register name="MM5" offset="0x1128" bitsize="64" />
<register name="MM6" offset="0x1130" bitsize="64" />
<register name="MM7" offset="0x1138" bitsize="64" />
<register name="XMM0" offset="0x1200" bitsize="128" />
<register name="XMM1" offset="0x1210" bitsize="128" />
<register name="XMM2" offset="0x1220" bitsize="128" />
<register name="XMM3" offset="0x1230" bitsize="128" />
<register name="XMM4" offset="0x1240" bitsize="128" />
<register name="XMM5" offset="0x1250" bitsize="128" />
<register name="XMM6" offset="0x1260" bitsize="128" />
<register name="XMM7" offset="0x1270" bitsize="128" />
<register name="XMM8" offset="0x1280" bitsize="128" />
<register name="XMM9" offset="0x1290" bitsize="128" />
<register name="XMM10" offset="0x12a0" bitsize="128" />
<register name="XMM11" offset="0x12b0" bitsize="128" />
<register name="XMM12" offset="0x12c0" bitsize="128" />
<register name="XMM13" offset="0x12d0" bitsize="128" />
<register name="XMM14" offset="0x12e0" bitsize="128" />
<register name="XMM15" offset="0x12f0" bitsize="128" />
<register name="IDTR" offset="0x2200" bitsize="48" />
<register name="IDTR_Limit" offset="0x2200" bitsize="16" />
<register name="IDTR_Address" offset="0x2202" bitsize="32" />
<register name="GDTR" offset="0x2210" bitsize="48" />
<register name="GDTR_Limit" offset="0x2210" bitsize="16" />
<register name="GDTR_Address" offset="0x2212" bitsize="32" />
<register name="LDTR" offset="0x2220" bitsize="48" />
<register name="LDTR_Limit" offset="0x2220" bitsize="16" />
<register name="LDTR_Address" offset="0x2222" bitsize="32" />
<register name="TR" offset="0x2230" bitsize="48" />
<register name="TR_Limit" offset="0x2230" bitsize="16" />
<register name="TR_Address" offset="0x2232" bitsize="32" />
</registers>
</language>

7
src/icicle/data/Ghidra/Processors/x86/data/languages/old/x86smmV1.trans Normal file
View File

@@ -0,0 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">x86:LE:32:System Management Mode</from_language>
<to_language version="2">x86:LE:32:System Management Mode</to_language>
<map_compiler_spec from="default" to="default" />
</language_translation>

173
src/icicle/data/Ghidra/Processors/x86/data/languages/pclmulqdq.sinc Normal file
View File

@@ -0,0 +1,173 @@
# Due to limitations on variable length matching that preclude opcode matching afterwards, all memory addressing forms of PCLMULQDQ are decoded to PCLMULQDQ, not the macro names.
# Display is non-standard, but semantics, and de-compilation should be correct.
macro pclmul(src1, src2, dest) {
local i:4 = 0:4;
local temp:16 = 0;
<start>
if (i > 63:4) goto <end>;
if ((src1 & (1 << i)) == 0) goto <skip>;
temp = temp ^ (src2 << i);
<skip>
i = i+1;
goto <start>;
<end>
dest = temp;
}
:PCLMULLQLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x00
{
local src1:16 = zext(XmmReg1[0,64]);
local src2:16 = zext(XmmReg2[0,64]);
pclmul(src1,src2,XmmReg1);
}
:PCLMULHQLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x01
{
local src1:16 = zext(XmmReg1[64,64]);
local src2:16 = zext(XmmReg2[0,64]);
pclmul(src1,src2,XmmReg1);
}
:PCLMULLQHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x10
{
local src1:16 = zext(XmmReg1[0,64]);
local src2:16 = zext(XmmReg2[64,64]);
pclmul(src1,src2,XmmReg1);
}
:PCLMULHQHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x11
{
local src1:16 = zext(XmmReg1[64,64]);
local src2:16 = zext(XmmReg2[64,64]);
pclmul(src1,src2,XmmReg1);
}
:PCLMULQDQ XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; imm8 & imm8_4 & imm8_0
{
if (imm8_0:1) goto <src1_b>;
src1:16 = zext(XmmReg1[0,64]);
goto <done1>;
<src1_b>
src1 = zext(XmmReg1[64,64]);
<done1>
if (imm8_4:1) goto <src2_b>;
src2:16 = zext(XmmReg2[0,64]);
goto <done2>;
<src2_b>
src2 = zext(XmmReg2[64,64]);
<done2>
pclmul(src1,src2,XmmReg1);
}
:PCLMULQDQ XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; XmmReg ... & m128; imm8 & imm8_4 & imm8_0
{
if (imm8_0:1) goto <src1_b>;
src1:16 = zext(XmmReg[0,64]);
goto <done1>;
<src1_b>
src1 = zext(XmmReg[64,64]);
<done1>
local m:16 = m128;
if (imm8_4:1) goto <src2_b>;
src2:16 = zext(m[0,64]);
goto <done2>;
<src2_b>
src2 = zext(m[64,64]);
<done2>
pclmul(src1,src2,XmmReg);
}
:VPCLMULLQLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x00
{
local src1:16 = zext(vexVVVV_XmmReg[0,64]);
local src2:16 = zext(XmmReg2[0,64]);
pclmul(src1,src2,XmmReg1);
YmmReg1 = zext(XmmReg1);
}
:VPCLMULHQLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x01
{
local src1:16 = zext(vexVVVV_XmmReg[64,64]);
local src2:16 = zext(XmmReg2[0,64]);
pclmul(src1,src2,XmmReg1);
YmmReg1 = zext(XmmReg1);
}
:VPCLMULLQHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x10
{
local src1:16 = zext(vexVVVV_XmmReg[0,64]);
local src2:16 = zext(XmmReg2[64,64]);
pclmul(src1,src2,XmmReg1);
YmmReg1 = zext(XmmReg1);
}
:VPCLMULHQHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x11
{
local src1:16 = zext(vexVVVV_XmmReg[64,64]);
local src2:16 = zext(XmmReg2[64,64]);
pclmul(src1,src2,XmmReg1);
YmmReg1 = zext(XmmReg1);
}
:VPCLMULQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; imm8 & imm8_4 & imm8_0
{
if (imm8_0:1) goto <src1_b>;
src1:16 = zext(vexVVVV_XmmReg[0,64]);
goto <done1>;
<src1_b>
src1 = zext(vexVVVV_XmmReg[64,64]);
<done1>
if (imm8_4:1) goto <src2_b>;
src2:16 = zext(XmmReg2[0,64]);
goto <done2>;
<src2_b>
src2 = zext(XmmReg2[64,64]);
<done2>
pclmul(src1,src2,XmmReg1);
YmmReg1 = zext(XmmReg1);
}
:VPCLMULQDQ XmmReg1, vexVVVV_XmmReg, m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; (XmmReg1 & YmmReg1) ... & m128; imm8 & imm8_4 & imm8_0
{
if (imm8_0:1) goto <src1_b>;
src1:16 = zext(vexVVVV_XmmReg[0,64]);
goto <done1>;
<src1_b>
src1 = zext(vexVVVV_XmmReg[64,64]);
<done1>
local m:16 = m128;
if (imm8_4:1) goto <src2_b>;
src2:16 = zext(m[0,64]);
goto <done2>;
<src2_b>
src2 = zext(m[64,64]);
<done2>
pclmul(src1,src2,XmmReg1);
YmmReg1 = zext(XmmReg1);
}

51
src/icicle/data/Ghidra/Processors/x86/data/languages/rdrand.sinc Normal file
View File

@@ -0,0 +1,51 @@
define pcodeop rdrand;
define pcodeop rdrandIsValid;
macro rdflags(){
OF = 0; SF = 0; ZF = 0; AF = 0; PF = 0;
}
:RDRAND Rmr16 is vexMode=0 & opsize=0 & byte=0x0f; byte=0xC7; mod=3 & Rmr16 & reg_opcode=6
{
Rmr16 = rdrand();
CF=rdrandIsValid();
rdflags();
}
:RDRAND Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & reg_opcode=6
{
Rmr32 = rdrand();
CF=rdrandIsValid();
rdflags();
}
@ifdef IA64
:RDRAND Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; mod=3 & Rmr64 & reg_opcode=6
{
Rmr64 = rdrand();
CF=rdrandIsValid();
rdflags();
}
@endif
define pcodeop rdseed;
define pcodeop rdseedIsValid;
:RDSEED Rmr16 is vexMode=0 & opsize=0 & byte=0x0f; byte=0xC7; mod=3 & Rmr16 & reg_opcode=7
{
Rmr16 = rdseed();
CF=rdseedIsValid();
rdflags();
}
:RDSEED Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & reg_opcode=7
{
Rmr32 = rdseed();
CF=rdseedIsValid();
rdflags();
}
@ifdef IA64
:RDSEED Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; mod=3 & Rmr64 & reg_opcode=7
{
Rmr64 = rdseed();
CF=rdseedIsValid();
rdflags();
}
@endif

257
src/icicle/data/Ghidra/Processors/x86/data/languages/sgx.sinc Normal file
View File

@@ -0,0 +1,257 @@
define pcodeop encls_ecreate;
define pcodeop encls_eadd;
define pcodeop encls_einit;
define pcodeop encls_einit_ZF;
define pcodeop encls_eremove;
define pcodeop encls_eremove_ZF;
define pcodeop encls_edbgrd;
define pcodeop encls_edbgrd_RBX;
define pcodeop encls_edbgwr;
define pcodeop encls_eextend;
define pcodeop encls_eldb;
define pcodeop encls_eldb_ZF;
define pcodeop encls_eldu;
define pcodeop encls_eldu_ZF;
define pcodeop encls_eblock;
define pcodeop encls_eblock_ZF;
define pcodeop encls_epa;
define pcodeop encls_ewb;
define pcodeop encls_ewb_ZF;
define pcodeop encls_ewb_CF;
define pcodeop encls_etrack;
define pcodeop encls_etrack_ZF;
define pcodeop encls_eaug;
define pcodeop encls_emodpr;
define pcodeop encls_emodpr_ZF;
define pcodeop encls_emodt;
define pcodeop encls_emodt_ZF;
define pcodeop encls_unknown;
:ENCLS is vexMode=0 & byte=0x0f; byte=0x01; byte=0xcf {
if ( EAX != 0x0 ) goto <leaf_1>;
encls_ecreate( RBX, RCX );
goto <done>;
<leaf_1>
if ( EAX != 0x1 ) goto <leaf_2>;
encls_eadd( RBX, RCX );
goto <done>;
<leaf_2>
if ( EAX != 0x2 ) goto <leaf_3>;
RAX = encls_einit( RBX, RCX, RDX );
ZF = encls_einit_ZF( RBX, RCX, RDX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_3>
if ( EAX != 0x3 ) goto <leaf_4>;
RAX = encls_eremove( RCX );
ZF = encls_eremove_ZF( RBX, RCX, RDX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_4>
if ( EAX != 0x4 ) goto <leaf_5>;
RAX = encls_edbgrd( RCX );
RBX = encls_edbgrd_RBX( RCX );
goto <done>;
<leaf_5>
if ( EAX != 0x5 ) goto <leaf_6>;
RAX = encls_edbgwr( RBX, RCX );
goto <done>;
<leaf_6>
if ( EAX != 0x6 ) goto <leaf_7>;
encls_eextend( RBX, RCX );
goto <done>;
<leaf_7>
if ( EAX != 0x7 ) goto <leaf_8>;
RAX = encls_eldb( RBX, RCX, RDX );
ZF = encls_eldb_ZF( RBX, RCX, RDX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_8>
if ( EAX != 0x8 ) goto <leaf_9>;
RAX = encls_eldu( RBX, RCX, RDX );
ZF = encls_eldu_ZF( RBX, RCX, RDX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_9>
if ( EAX != 0x9 ) goto <leaf_A>;
RAX = encls_eblock( RCX );
ZF = encls_eblock_ZF( RCX );
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_A>
if ( EAX != 0xA ) goto <leaf_B>;
encls_epa( RBX, RCX );
goto <done>;
<leaf_B>
if ( EAX != 0xB ) goto <leaf_C>;
RAX = encls_ewb( RBX, RCX, RDX );
ZF = encls_ewb_ZF( RBX, RCX, RDX );
CF = encls_ewb_CF( RBX, RCX, RDX );
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_C>
if ( EAX != 0xC ) goto <leaf_D>;
RAX = encls_etrack( RCX );
ZF = encls_etrack_ZF( RBX, RCX, RDX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_D>
if ( EAX != 0xD ) goto <leaf_E>;
encls_eaug( RBX, RCX, RDX );
goto <done>;
<leaf_E>
if ( EAX != 0xE ) goto <leaf_F>;
RAX = encls_emodpr( RBX, RCX );
ZF = encls_emodpr_ZF( RCX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_F>
if ( EAX != 0xF ) goto <unknown>;
RAX = encls_emodt( RBX, RCX );
ZF = encls_emodt_ZF( RCX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<unknown>
encls_unknown();
<done>
}
define pcodeop enclu_ereport;
define pcodeop enclu_egetkey;
define pcodeop enclu_egetkey_ZF;
define pcodeop enclu_eenter_EAX;
define pcodeop enclu_eenter_RCX;
define pcodeop enclu_eenter_TF;
define pcodeop enclu_eresume;
define pcodeop enclu_eexit;
define pcodeop enclu_eexit_TF;
define pcodeop enclu_eaccept;
define pcodeop enclu_eaccept_ZF;
define pcodeop enclu_emodpe;
define pcodeop enclu_eacceptcopy;
define pcodeop enclu_eacceptcopy_ZF;
define pcodeop enclu_unknown;
:ENCLU is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd7 {
if ( EAX != 0x0 ) goto <leaf_1>;
enclu_ereport( RBX, RCX, RDX );
goto <done>;
<leaf_1>
if ( EAX != 0x1 ) goto <leaf_2>;
RAX = enclu_egetkey( RBX, RCX );
ZF = enclu_egetkey_ZF( RBX, RCX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_2>
if ( EAX != 0x2 ) goto <leaf_3>;
tempBX:8 = RBX;
tempCX:8 = RCX;
EAX = enclu_eenter_EAX( tempBX, tempCX );
RCX = enclu_eenter_RCX( tempBX, tempCX );
TF = enclu_eenter_TF( tempBX, tempCX );
goto <done>;
<leaf_3>
if ( EAX != 0x3 ) goto <leaf_4>;
TF = enclu_eresume( RBX, RCX );
goto <done>;
<leaf_4>
if ( EAX != 0x4 ) goto <leaf_5>;
RCX = enclu_eexit( RBX );
TF = enclu_eexit_TF( RBX );
goto <done>;
<leaf_5>
if ( EAX != 0x5 ) goto <leaf_6>;
RAX = enclu_eaccept( RBX, RCX );
ZF = enclu_eaccept_ZF( RBX, RCX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<leaf_6>
if ( EAX != 0x6 ) goto <leaf_7>;
enclu_emodpe( RBX, RCX );
goto <done>;
<leaf_7>
if ( EAX != 0x7 ) goto <unknown>;
RAX = enclu_eacceptcopy( RBX, RCX, RDX );
ZF = enclu_eacceptcopy_ZF( RBX, RCX, RDX );
CF = 0;
PF = 0;
AF = 0;
OF = 0;
SF = 0;
goto <done>;
<unknown>
enclu_unknown();
<done>
}

53
src/icicle/data/Ghidra/Processors/x86/data/languages/sha.sinc Normal file
View File

@@ -0,0 +1,53 @@
# INFO This file automatically generated by andre on Fri Mar 16 15:13:25 2018
# INFO Direct edits to this file may be lost in future updates
# INFO Command line arguments: ['--sinc', '--cpuid-match', 'SHA']
# SHA1RNDS4 4-602 PAGE 1722 LINE 89511
define pcodeop sha1rnds4_sha ;
:SHA1RNDS4 XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & byte=0x0F; byte=0x3A; byte=0xCC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8
{
XmmReg1 = sha1rnds4_sha( XmmReg1, XmmReg2_m128, imm8:1 );
}
# SHA1NEXTE 4-604 PAGE 1724 LINE 89602
define pcodeop sha1nexte_sha ;
:SHA1NEXTE XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xC8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha1nexte_sha( XmmReg1, XmmReg2_m128 );
}
# SHA1MSG1 4-605 PAGE 1725 LINE 89654
define pcodeop sha1msg1_sha ;
:SHA1MSG1 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xC9; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha1msg1_sha( XmmReg1, XmmReg2_m128 );
}
# SHA1MSG2 4-606 PAGE 1726 LINE 89708
define pcodeop sha1msg2_sha ;
:SHA1MSG2 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha1msg2_sha( XmmReg1, XmmReg2_m128 );
}
# SHA256RNDS2 4-607 PAGE 1727 LINE 89765
define pcodeop sha256rnds2_sha ;
:SHA256RNDS2 XmmReg1, XmmReg2_m128, XMM0 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCB; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 & XMM0
{
XmmReg1 = sha256rnds2_sha( XmmReg1, XmmReg2_m128, XMM0 );
}
# SHA256MSG1 4-609 PAGE 1729 LINE 89847
define pcodeop sha256msg1_sha ;
:SHA256MSG1 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha256msg1_sha( XmmReg1, XmmReg2_m128 );
}
# SHA256MSG2 4-610 PAGE 1730 LINE 89900
define pcodeop sha256msg2_sha ;
:SHA256MSG2 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCD; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha256msg2_sha( XmmReg1, XmmReg2_m128 );
}

67
src/icicle/data/Ghidra/Processors/x86/data/languages/smx.sinc Normal file
View File

@@ -0,0 +1,67 @@
define pcodeop getsec_capabilities;
define pcodeop getsec_enteraccs;
define pcodeop getsec_exitac;
define pcodeop getsec_senter;
define pcodeop getsec_sexit;
define pcodeop getsec_parameters_EAX;
define pcodeop getsec_parameters_EBX;
define pcodeop getsec_parameters_ECX;
define pcodeop getsec_smctrl;
define pcodeop getsec_wakeup;
define pcodeop getsec_unknown;
:GETSEC is vexMode=0 & byte=0x0f; byte=0x37 {
if ( EAX != 0x0 ) goto <leaf_1>;
EAX = 0;
if ( EBX != 0x0 ) goto <done>;
EAX = getsec_capabilities( EBX );
goto <done>;
<leaf_1>
if ( EAX != 0x2 ) goto <leaf_2>;
getsec_enteraccs( EBX, ECX );
goto <done>;
<leaf_2>
if ( EAX != 0x3 ) goto <leaf_3>;
@ifdef IA64
getsec_exitac( RBX, EDX );
@else
getsec_exitac( EBX, EDX );
@endif
goto <done>;
<leaf_3>
if ( EAX != 0x4 ) goto <leaf_4>;
getsec_senter( EBX, ECX, EDX);
goto <done>;
<leaf_4>
if ( EAX != 0x5 ) goto <leaf_5>;
getsec_sexit();
goto <done>;
<leaf_5>
if ( EAX != 0x6 ) goto <leaf_6>;
EAX = getsec_parameters_EAX( EBX );
ECX = getsec_parameters_ECX( EBX );
EBX = getsec_parameters_EBX( EBX );
goto <done>;
<leaf_6>
if ( EAX != 0x7 ) goto <leaf_7>;
getsec_smctrl(EBX);
goto <done>;
<leaf_7>
if ( EAX != 0x8 ) goto <unknown>;
getsec_wakeup();
goto <done>;
<unknown>
getsec_unknown();
<done>
}

33
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-16-real.pspec Normal file
View File

@@ -0,0 +1,33 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Set up x86 16-bit in real mode -->
<processor_spec>
<properties>
<property key="useOperandReferenceAnalyzerSwitchTables" value="true"/>
</properties>
<programcounter register="EIP"/>
<segmented_address space="ram" type="real" />
<segmentop space="ram" userop="segment" farpointer="yes">
<pcode>
<input name="base" size="2"/>
<input name="inner" size="2"/>
<output name="res" size="4"/>
<body><![CDATA[
res = (zext(base) << 4) + zext(inner);
]]></body>
</pcode>
<constresolve>
<register name="DS"/>
</constresolve>
</segmentop>
<context_data>
<context_set space="ram">
<set name="addrsize" val="0"/>
<set name="opsize" val="0"/>
<set name="protectedMode" val="0"/>
</context_set>
<tracked_set space="ram">
<set name="DF" val="0"/>
</tracked_set>
</context_data>
</processor_spec>

174
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-16.cspec Normal file
View File

@@ -0,0 +1,174 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" /> <!-- no maximum alignment -->
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="2" />
<pointer_size value="2" /> <!-- near pointer, TODO: how do we define far 4-byte pointer? -->
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="2" />
<long_size value="4" />
<long_long_size value="4" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="10" />
<!-- alignment varies between MIcrosoft and Borland -->
<!--
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="2" />
<entry size="8" alignment="2" />
</size_alignment_map>
-->
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram"/>
<default_proto>
<prototype name="__stdcall16near" extrapop="unknown" stackshift="2">
<input>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="AX"/>
</pentry>
<pentry minsize="3" maxsize="4">
<addr space="join" piece1="DX" piece2="AX"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="BP"/>
<register name="SI"/>
<register name="DI"/>
<register name="DS"/>
<register name="CS"/>
<register name="ES"/>
<register name="SS"/>
<register name="DF"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="__cdecl16near" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="AX"/>
</pentry>
<pentry minsize="3" maxsize="4">
<addr space="join" piece1="DX" piece2="AX"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="BP"/>
<register name="SI"/>
<register name="DI"/>
<register name="DS"/>
<register name="CS"/>
<register name="ES"/>
<register name="SS"/>
<register name="DF"/>
</unaffected>
</prototype>
<prototype name="__stdcall16far" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="AX"/>
</pentry>
<pentry minsize="3" maxsize="4">
<addr space="join" piece1="DX" piece2="AX"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="BP"/>
<register name="SI"/>
<register name="DI"/>
<register name="DS"/>
<register name="CS"/>
<register name="ES"/>
<register name="SS"/>
<register name="DF"/>
</unaffected>
</prototype>
<prototype name="__cdecl16far" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="AX"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="BP"/>
<register name="SI"/>
<register name="DI"/>
<register name="DS"/>
<register name="CS"/>
<register name="ES"/>
<register name="SS"/>
<register name="DF"/>
</unaffected>
</prototype>
<prototype name="__regcall" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="2">
<register name="AX"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BX"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="CX"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DX"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="AX"/>
</pentry>
<pentry minsize="3" maxsize="4">
<addr space="join" piece1="DX" piece2="AX"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="BP"/>
<register name="CX"/>
<register name="DX"/>
<register name="SI"/>
<register name="DI"/>
<register name="DS"/>
<register name="CS"/>
<register name="ES"/>
<register name="SS"/>
<register name="DF"/>
</unaffected>
</prototype>
</compiler_spec>

3
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-16.gdis Normal file
View File

@@ -0,0 +1,3 @@
<gdis>
<global optstring="intel"/>
</gdis>

34
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-16.pspec Normal file
View File

@@ -0,0 +1,34 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Set up x86 16-bit in protected mode -->
<processor_spec>
<properties>
<property key="useOperandReferenceAnalyzerSwitchTables" value="true"/>
</properties>
<programcounter register="EIP"/>
<segmented_address space="ram" type="protected"/>
<segmentop space="ram" userop="segment" farpointer="yes">
<pcode>
<input name="base" size="2"/>
<input name="inner" size="2"/>
<output name="res" size="4"/>
<body><![CDATA[
res = (zext(base) << 16) + zext(inner);
]]></body>
</pcode>
<constresolve>
<register name="DS"/>
</constresolve>
</segmentop>
<context_data>
<context_set space="ram">
<set name="addrsize" val="0"/>
<set name="opsize" val="0"/>
<set name="protectedMode" val="1"/>
</context_set>
<tracked_set space="ram">
<set name="DF" val="0"/>
</tracked_set>
</context_data>
</processor_spec>

242
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-64-gcc.cspec Normal file
View File

@@ -0,0 +1,242 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="8" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="8" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="10" /> <!-- aligned-length=16 -->
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
<entry size="16" alignment="16" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="RSP" space="ram"/>
<returnaddress>
<varnode space="stack" offset="0" size="8"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="8" stackshift="8">
<!-- Derived from "System V Application Binary Interface AMD64 Architecture Processor Supplement" April 2016 -->
<input>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM0_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM1_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM2_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM3_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM4_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM5_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM6_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM7_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RDI"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RSI"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RDX"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RCX"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R8"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R9"/>
</pentry>
<pentry minsize="1" maxsize="500" align="8">
<addr offset="8" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM0_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RAX"/>
</pentry>
<pentry minsize="9" maxsize="16">
<addr space="join" piece1="RDX" piece2="RAX"/>
</pentry>
</output>
<killedbycall>
<register name="RAX"/>
<register name="RDX"/>
<register name="XMM0"/>
</killedbycall>
<unaffected>
<register name="RBX"/>
<register name="RSP"/>
<register name="RBP"/>
<register name="R12"/>
<register name="R13"/>
<register name="R14"/>
<register name="R15"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="MSABI" extrapop="8" stackshift="8">
<input pointermax="8">
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM0_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM1_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM2_Qa"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM3_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RCX"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RDX"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R8"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R9"/>
</pentry>
<pentry minsize="1" maxsize="500" align="8">
<addr offset="40" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM0_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="8"/>
<register name="RBX"/>
<register name="RBP"/>
<register name="RDI"/>
<register name="RSI"/>
<register name="RSP"/>
<register name="R12"/>
<register name="R13"/>
<register name="R14"/>
<register name="R15"/>
<register name="DF"/>
</unaffected>
<killedbycall>
<register name="RAX"/>
<register name="XMM0"/>
</killedbycall>
<localrange>
<range space="stack" first="0xfffffffffff0bdc1" last="0xffffffffffffffff"/>
<range space="stack" first="8" last="39"/>
</localrange>
</prototype>
<prototype name="syscall" extrapop="8" stackshift="8">
<input pointermax="8">
<pentry minsize="1" maxsize="8">
<register name="RDI"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RSI"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RDX"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R10"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R8"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R9"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="8">
<register name="RAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="8"/>
<register name="RBX"/>
<register name="RDX"/>
<register name="RBP"/>
<register name="RDI"/>
<register name="RSI"/>
<register name="RSP"/>
<register name="R8"/>
<register name="R9"/>
<register name="R10"/>
<register name="R12"/>
<register name="R13"/>
<register name="R14"/>
<register name="R15"/>
<register name="DF"/>
</unaffected>
<killedbycall>
<register name="RCX"/>
<register name="R11"/>
</killedbycall>
</prototype>
<prototype name="processEntry" extrapop="0" stackshift="0">
<input pointermax="8">
<pentry minsize="1" maxsize="8">
<register name="RDX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="8">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="8">
<register name="RAX"/>
</pentry>
</output>
<unaffected>
<register name="RSP"/>
</unaffected>
<!-- Functions with this prototype don't have a return address. But, if we don't specify one, this prototype will
use the default, which is to have the return address on the stack. That conflicts with how this prototype actually
uses the stack, so we set a fake return address at a RBP, which is unspecified at process entry -->
<returnaddress>
<register name="RBP"/>
</returnaddress>
</prototype>
</compiler_spec>

224
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-64-win.cspec Normal file
View File

@@ -0,0 +1,224 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- see: -->
<!-- https://docs.microsoft.com/en-us/cpp/build/x64-software-conventions#register-usage -->
<!-- https://docs.microsoft.com/en-us/cpp/build/x64-calling-convention -->
<!-- https://docs.microsoft.com/en-us/cpp/c-runtime-library/direction-flag -->
<!-- https://docs.microsoft.com/en-us/cpp/cpp/vectorcall -->
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="8" />
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
<bitfield_packing>
<use_MS_convention value="true"/>
</bitfield_packing>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="RSP" space="ram"/>
<returnaddress>
<varnode space="stack" offset="0" size="8"/>
</returnaddress>
<default_proto>
<prototype name="__fastcall" extrapop="8" stackshift="8">
<input pointermax="8">
<group>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM0_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RCX"/>
</pentry>
</group>
<group>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM1_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RDX"/>
</pentry>
</group>
<group>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM2_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R8"/>
</pentry>
</group>
<group>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM3_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R9"/>
</pentry>
</group>
<pentry minsize="1" maxsize="500" align="8">
<addr offset="40" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM0_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="8"/>
<register name="RBX"/>
<register name="RBP"/>
<register name="RDI"/>
<register name="RSI"/>
<register name="RSP"/>
<register name="R12"/>
<register name="R13"/>
<register name="R14"/>
<register name="R15"/>
<register name="DF"/>
<register name="GS_OFFSET"/>
<register name="XMM6"/>
<register name="XMM7"/>
<register name="XMM8"/>
<register name="XMM9"/>
<register name="XMM10"/>
<register name="XMM11"/>
<register name="XMM12"/>
<register name="XMM13"/>
<register name="XMM14"/>
<register name="XMM15"/>
</unaffected>
<killedbycall>
<register name="RAX"/>
<register name="XMM0"/>
</killedbycall>
<localrange>
<range space="stack" first="0xfffffffffff0bdc1" last="0xffffffffffffffff"/>
<range space="stack" first="8" last="39"/>
</localrange>
</prototype>
</default_proto>
<prototype name="__thiscall" extrapop="8" stackshift="8">
<input pointermax="8" thisbeforeretpointer="true">
<group>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM0_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RCX"/>
</pentry>
</group>
<group>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM1_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RDX"/>
</pentry>
</group>
<group>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM2_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R8"/>
</pentry>
</group>
<group>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM3_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="R9"/>
</pentry>
</group>
<pentry minsize="1" maxsize="500" align="8">
<addr offset="40" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="XMM0_Qa"/>
</pentry>
<pentry minsize="1" maxsize="8">
<register name="RAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="8"/>
<register name="RBX"/>
<register name="RBP"/>
<register name="RDI"/>
<register name="RSI"/>
<register name="RSP"/>
<register name="R12"/>
<register name="R13"/>
<register name="R14"/>
<register name="R15"/>
<register name="DF"/>
<register name="GS_OFFSET"/>
<register name="XMM6"/>
<register name="XMM7"/>
<register name="XMM8"/>
<register name="XMM9"/>
<register name="XMM10"/>
<register name="XMM11"/>
<register name="XMM12"/>
<register name="XMM13"/>
<register name="XMM14"/>
<register name="XMM15"/>
</unaffected>
<killedbycall>
<register name="RAX"/>
<register name="XMM0"/>
</killedbycall>
<localrange>
<range space="stack" first="0xfffffffffff0bdc1" last="0xffffffffffffffff"/>
<range space="stack" first="8" last="39"/>
</localrange>
</prototype>
<modelalias name="__cdecl" parent="__fastcall"/>
<callfixup name="alloca_probe">
<target name="_alloca_probe"/>
<target name="_alloca_probe2"/>
<target name="__chkstk"/>
<target name="__chkstk2"/>
<target name="___chkstk_ms"/>
<pcode>
<body><![CDATA[
RSP = RSP + 0;
]]></body>
</pcode>
</callfixup>
<callfixup name="guard_dispatch_icall">
<target name="_guard_dispatch_icall"/>
<pcode>
<body><![CDATA[
call [RAX];
]]></body>
</pcode>
</callfixup>
</compiler_spec>

34
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-64.dwarf Normal file
View File

@@ -0,0 +1,34 @@
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="RAX"/>
<register_mapping dwarf="1" ghidra="RDX"/>
<register_mapping dwarf="2" ghidra="RCX"/>
<register_mapping dwarf="3" ghidra="RBX"/>
<register_mapping dwarf="4" ghidra="RSI"/>
<register_mapping dwarf="5" ghidra="RDI"/>
<register_mapping dwarf="6" ghidra="RBP"/>
<register_mapping dwarf="7" ghidra="RSP" stackpointer="true"/>
<register_mapping dwarf="8" ghidra="R8" auto_count="8"/> <!-- R8..R15 -->
<register_mapping dwarf="16" ghidra="RIP"/>
<register_mapping dwarf="17" ghidra="XMM0" auto_count="16"/> <!-- XMM0..XMM15 -->
<register_mapping dwarf="33" ghidra="ST0" auto_count="8"/> <!-- ST0..ST7 -->
<register_mapping dwarf="41" ghidra="MM0" auto_count="8"/> <!-- MM0..MM7 -->
<register_mapping dwarf="49" ghidra="rflags"/>
<register_mapping dwarf="50" ghidra="ES"/>
<register_mapping dwarf="51" ghidra="CS"/>
<register_mapping dwarf="52" ghidra="SS"/>
<register_mapping dwarf="53" ghidra="DS"/>
<register_mapping dwarf="54" ghidra="FS"/>
<register_mapping dwarf="55" ghidra="GS"/>
<!-- <register_mapping dwarf="58" ghidra="FSBASE"/> **not implemented** -->
<!-- <register_mapping dwarf="59" ghidra="GSBASE"/> **not implemented** -->
<register_mapping dwarf="62" ghidra="TR"/>
<register_mapping dwarf="63" ghidra="LDTR"/>
<register_mapping dwarf="64" ghidra="MXCSR"/>
<!-- <register_mapping dwarf="65" ghidra="FCW"/> **not implemented** -->
<!-- <register_mapping dwarf="66" ghidra="FSW"/> **not implemented** -->
<!-- <register_mapping dwarf="68" ghidra="XMM16" auto_count="16"/> **not implemented yet** --> <!-- XMM16..XMM31 -->
<!-- <register_mapping dwarf="118" ghidra="K0" auto_count="8"/> **not implemented yet** -->
</register_mappings>
<call_frame_cfa value="8"/>
</dwarf>

160
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-64.pspec Normal file
View File

@@ -0,0 +1,160 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="useOperandReferenceAnalyzerSwitchTables" value="true"/>
<property key="assemblyRating:x86:LE:64:default" value="GOLD"/>
</properties>
<programcounter register="RIP"/>
<context_data>
<context_set space="ram">
<set name="addrsize" val="2"/>
<set name="bit64" val="1"/>
<set name="opsize" val="1"/>
<set name="rexprefix" val="0"/>
<set name="longMode" val="1"/>
</context_set>
<tracked_set space="ram">
<set name="DF" val="0"/>
</tracked_set>
</context_data>
<register_data>
<register name="DR0" group="DEBUG"/>
<register name="DR1" group="DEBUG"/>
<register name="DR2" group="DEBUG"/>
<register name="DR3" group="DEBUG"/>
<register name="DR4" group="DEBUG"/>
<register name="DR5" group="DEBUG"/>
<register name="DR6" group="DEBUG"/>
<register name="DR7" group="DEBUG"/>
<register name="DR8" group="DEBUG"/>
<register name="DR9" group="DEBUG"/>
<register name="DR10" group="DEBUG"/>
<register name="DR11" group="DEBUG"/>
<register name="DR12" group="DEBUG"/>
<register name="DR13" group="DEBUG"/>
<register name="DR14" group="DEBUG"/>
<register name="DR15" group="DEBUG"/>
<register name="CR0" group="CONTROL"/>
<register name="CR1" group="CONTROL"/>
<register name="CR2" group="CONTROL"/>
<register name="CR3" group="CONTROL"/>
<register name="CR4" group="CONTROL"/>
<register name="CR5" group="CONTROL"/>
<register name="CR6" group="CONTROL"/>
<register name="CR7" group="CONTROL"/>
<register name="CR8" group="CONTROL"/>
<register name="CR9" group="CONTROL"/>
<register name="CR10" group="CONTROL"/>
<register name="CR11" group="CONTROL"/>
<register name="CR12" group="CONTROL"/>
<register name="CR13" group="CONTROL"/>
<register name="CR14" group="CONTROL"/>
<register name="CR15" group="CONTROL"/>
<register name="C0" group="Cx"/>
<register name="C1" group="Cx"/>
<register name="C2" group="Cx"/>
<register name="C3" group="Cx"/>
<register name="ST0" group="ST"/>
<register name="ST1" group="ST"/>
<register name="ST2" group="ST"/>
<register name="ST3" group="ST"/>
<register name="ST4" group="ST"/>
<register name="ST5" group="ST"/>
<register name="ST6" group="ST"/>
<register name="ST7" group="ST"/>
<register name="FPUControlWord" group="FPU"/>
<register name="FPUStatusWord" group="FPU"/>
<register name="FPUTagWord" group="FPU"/>
<register name="FPUDataPointer" group="FPU"/>
<register name="FPUInstructionPointer" group="FPU"/>
<register name="FPULastInstructionOpcode" group="FPU"/>
<register name="MM0" group="MMX"/>
<register name="MM1" group="MMX"/>
<register name="MM2" group="MMX"/>
<register name="MM3" group="MMX"/>
<register name="MM4" group="MMX"/>
<register name="MM5" group="MMX"/>
<register name="MM6" group="MMX"/>
<register name="MM7" group="MMX"/>
<register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" vector_lane_sizes="1,2,4,8"/>
<register name="CF" group="FLAGS"/>
<register name="F1" group="FLAGS"/>
<register name="PF" group="FLAGS"/>
<register name="F3" group="FLAGS"/>
<register name="AF" group="FLAGS"/>
<register name="F5" group="FLAGS"/>
<register name="ZF" group="FLAGS"/>
<register name="SF" group="FLAGS"/>
<register name="TF" group="FLAGS"/>
<register name="IF" group="FLAGS"/>
<register name="DF" group="FLAGS"/>
<register name="OF" group="FLAGS"/>
<register name="IOPL" group="FLAGS"/>
<register name="NT" group="FLAGS"/>
<register name="F15" group="FLAGS"/>
<register name="RF" group="FLAGS"/>
<register name="VM" group="FLAGS"/>
<register name="AC" group="FLAGS"/>
<register name="VIF" group="FLAGS"/>
<register name="VIP" group="FLAGS"/>
<register name="ID" group="FLAGS"/>
<register name="rflags" group="FLAGS"/>
<register name="eflags" group="FLAGS"/>
<register name="flags" group="FLAGS"/>
<register name="bit64" hidden="true"/>
<register name="segover" hidden="true"/>
<register name="repneprefx" hidden="true"/>
<register name="repprefx" hidden="true"/>
<register name="rexWprefix" hidden="true"/>
<register name="rexRprefix" hidden="true"/>
<register name="rexXprefix" hidden="true"/>
<register name="rexBprefix" hidden="true"/>
<register name="xmmTmp1" hidden="true"/>
<register name="xmmTmp1_Qa" hidden="true"/>
<register name="xmmTmp1_Da" hidden="true"/>
<register name="xmmTmp1_Db" hidden="true"/>
<register name="xmmTmp1_Qb" hidden="true"/>
<register name="xmmTmp1_Dc" hidden="true"/>
<register name="xmmTmp1_Dd" hidden="true"/>
<register name="xmmTmp2" hidden="true"/>
<register name="xmmTmp2_Qa" hidden="true"/>
<register name="xmmTmp2_Da" hidden="true"/>
<register name="xmmTmp2_Db" hidden="true"/>
<register name="xmmTmp2_Qb" hidden="true"/>
<register name="xmmTmp2_Dc" hidden="true"/>
<register name="xmmTmp2_Dd" hidden="true"/>
<register name="rexprefix" hidden="true"/>
</register_data>
</processor_spec>

6
src/icicle/data/Ghidra/Processors/x86/data/languages/x86-64.slaspec Normal file
View File

@@ -0,0 +1,6 @@
@define IA64 "IA64"
@include "x86.slaspec"
with : lockprefx=0 {
@include "sgx.sinc"
@include "fma.sinc"
}

34
src/icicle/data/Ghidra/Processors/x86/data/languages/x86.dwarf Normal file
View File

@@ -0,0 +1,34 @@
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="EAX"/>
<register_mapping dwarf="1" ghidra="ECX"/>
<register_mapping dwarf="2" ghidra="EDX"/>
<register_mapping dwarf="3" ghidra="EBX"/>
<register_mapping dwarf="4" ghidra="ESP" stackpointer="true"/>
<register_mapping dwarf="5" ghidra="EBP"/>
<register_mapping dwarf="6" ghidra="ESI"/>
<register_mapping dwarf="7" ghidra="EDI"/>
<register_mapping dwarf="8" ghidra="EIP"/>
<register_mapping dwarf="9" ghidra="eflags"/>
<!-- <register_mapping dwarf="10" ghidra="TRAPNO"/> **not implemented** -->
<register_mapping dwarf="11" ghidra="ST0" auto_count="8"/> <!-- ST0..ST7 -->
<register_mapping dwarf="21" ghidra="XMM0" auto_count="8"/> <!-- XMM0..XMM7 -->
<register_mapping dwarf="29" ghidra="MM0" auto_count="8"/> <!-- MM0..MM7 -->
<!-- <register_mapping dwarf="37" ghidra="FCW"/> **not implemented** -->
<!-- <register_mapping dwarf="38" ghidra="FSW"/> **not implemented** -->
<register_mapping dwarf="39" ghidra="MXCSR"/>
<register_mapping dwarf="40" ghidra="ES"/>
<register_mapping dwarf="41" ghidra="CS"/>
<register_mapping dwarf="42" ghidra="SS"/>
<register_mapping dwarf="43" ghidra="DS"/>
<register_mapping dwarf="44" ghidra="FS"/>
<register_mapping dwarf="45" ghidra="GS"/>
<register_mapping dwarf="48" ghidra="TR"/>
<register_mapping dwarf="49" ghidra="LDTR"/>
</register_mappings>
<call_frame_cfa value="4"/>
</dwarf>

98
src/icicle/data/Ghidra/Processors/x86/data/languages/x86.ldefs Normal file
View File

@@ -0,0 +1,98 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="x86"
endian="little"
size="32"
variant="default"
version="2.14"
slafile="x86.sla"
processorspec="x86.pspec"
manualindexfile="../manuals/x86.idx"
id="x86:LE:32:default">
<description>Intel/AMD 32-bit x86</description>
<compiler name="Visual Studio" spec="x86win.cspec" id="windows"/>
<compiler name="clang" spec="x86win.cspec" id="clangwindows"/>
<compiler name="gcc" spec="x86gcc.cspec" id="gcc"/>
<compiler name="Borland C++" spec="x86borland.cspec" id="borlandcpp"/>
<compiler name="Delphi" spec="x86delphi.cspec" id="borlanddelphi"/>
<external_name tool="gnu" name="i386:intel"/>
<external_name tool="IDA-PRO" name="8086"/>
<external_name tool="IDA-PRO" name="80486p"/>
<external_name tool="IDA-PRO" name="80586p"/>
<external_name tool="IDA-PRO" name="80686p"/>
<external_name tool="IDA-PRO" name="k62"/>
<external_name tool="IDA-PRO" name="p2"/>
<external_name tool="IDA-PRO" name="p3"/>
<external_name tool="IDA-PRO" name="athlon"/>
<external_name tool="IDA-PRO" name="p4"/>
<external_name tool="IDA-PRO" name="metapc"/>
<external_name tool="DWARF.register.mapping.file" name="x86.dwarf"/>
</language>
<language processor="x86"
endian="little"
size="32"
variant="System Management Mode"
version="2.14"
slafile="x86.sla"
processorspec="x86-16.pspec"
manualindexfile="../manuals/x86.idx"
id="x86:LE:32:System Management Mode">
<description>Intel/AMD 32-bit x86 System Management Mode</description>
<compiler name="default" spec="x86-16.cspec" id="default"/>
<external_name tool="DWARF.register.mapping.file" name="x86.dwarf"/>
</language>
<language processor="x86"
endian="little"
size="16"
variant="Real Mode"
version="2.14"
slafile="x86.sla"
processorspec="x86-16-real.pspec"
manualindexfile="../manuals/x86.idx"
id="x86:LE:16:Real Mode">
<description>Intel/AMD 16-bit x86 Real Mode</description>
<compiler name="default" spec="x86-16.cspec" id="default"/>
<external_name tool="IDA-PRO" name="8086"/>
<external_name tool="IDA-PRO" name="8086r"/>
<external_name tool="IDA-PRO" name="80386r"/>
<external_name tool="IDA-PRO" name="80486r"/>
<external_name tool="IDA-PRO" name="80586r"/>
<external_name tool="IDA-PRO" name="metapc"/>
<external_name tool="gnu" name="i8086"/>
<external_name tool="gdis.disassembler.options.file" name="x86-16.gdis"/>
</language>
<language processor="x86"
endian="little"
size="16"
variant="Protected Mode"
version="2.14"
slafile="x86.sla"
processorspec="x86-16.pspec"
manualindexfile="../manuals/x86.idx"
id="x86:LE:16:Protected Mode">
<description>Intel/AMD 16-bit x86 Protected Mode</description>
<compiler name="default" spec="x86-16.cspec" id="default"/>
<external_name tool="IDA-PRO" name="8086p"/>
<external_name tool="gnu" name="i8086"/>
<external_name tool="gdis.disassembler.options.file" name="x86-16.gdis"/>
</language>
<language processor="x86"
endian="little"
size="64"
variant="default"
version="2.14"
slafile="x86-64.sla"
processorspec="x86-64.pspec"
manualindexfile="../manuals/x86.idx"
id="x86:LE:64:default">
<description>Intel/AMD 64-bit x86</description>
<compiler name="Visual Studio" spec="x86-64-win.cspec" id="windows"/>
<compiler name="clang" spec="x86-64-win.cspec" id="clangwindows"/>
<compiler name="gcc" spec="x86-64-gcc.cspec" id="gcc"/>
<external_name tool="gnu" name="i386:x86-64:intel"/>
<external_name tool="gnu" name="i386:x86-64"/>
<external_name tool="IDA-PRO" name="metapc"/>
<external_name tool="DWARF.register.mapping.file" name="x86-64.dwarf"/>
</language>
</language_definitions>

81
src/icicle/data/Ghidra/Processors/x86/data/languages/x86.opinion Normal file
View File

@@ -0,0 +1,81 @@
<opinions>
<constraint loader="Portable Executable (PE)">
<constraint compilerSpecID="windows">
<constraint primary="332" processor="x86" endian="little" size="32" />
<constraint primary="333" processor="x86" endian="little" size="32" />
<constraint primary="334" processor="x86" endian="little" size="32" />
<constraint primary="34404" processor="x86" endian="little" size="64" />
</constraint>
<constraint compilerSpecID="clangwindows">
<constraint primary="332" secondary="clang" processor="x86" endian="little" size="32" />
<constraint primary="333" secondary="clang" processor="x86" endian="little" size="32" />
<constraint primary="334" secondary="clang" processor="x86" endian="little" size="32" />
<constraint primary="34404" secondary="clang" processor="x86" endian="little" size="64" />
</constraint>
<constraint compilerSpecID="borlandcpp">
<constraint primary="332" secondary="borlandcpp" processor="x86" endian="little" size="32" />
<constraint primary="333" secondary="borlandcpp" processor="x86" endian="little" size="32" />
<constraint primary="334" secondary="borlandcpp" processor="x86" endian="little" size="32" />
</constraint>
<constraint compilerSpecID="borlanddelphi">
<constraint primary="332" secondary="borlanddelphi" processor="x86" endian="little" size="32" />
<constraint primary="333" secondary="borlanddelphi" processor="x86" endian="little" size="32" />
<constraint primary="334" secondary="borlanddelphi" processor="x86" endian="little" size="32" />
</constraint>
</constraint>
<constraint loader="Debug Symbols (DBG)" compilerSpecID="windows">
<constraint primary="332" processor="x86" endian="little" size="32" />
<constraint primary="333" processor="x86" endian="little" size="32" />
<constraint primary="334" processor="x86" endian="little" size="32" />
<constraint primary="34404" processor="x86" endian="little" size="64" />
</constraint>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="gcc">
<constraint primary="3" processor="x86" endian="little" size="32" />
<constraint primary="62" processor="x86" endian="little" size="64" />
</constraint>
<constraint loader="Module Definition (DEF)" compilerSpecID="windows">
<constraint primary="0" processor="x86" endian="little" size="32" />
</constraint>
<constraint loader="Program Mapfile (MAP)" compilerSpecID="windows">
<constraint primary="0" processor="x86" endian="little" size="32" />
</constraint>
<constraint loader="Old-style DOS Executable (MZ)" compilerSpecID="default">
<constraint primary="23117" processor="x86" endian="little" size="16" variant="Real Mode"/>
</constraint>
<constraint loader="New Executable (NE)" compilerSpecID="default">
<constraint primary="17742" processor="x86" endian="little" size="16" variant="Protected Mode"/>
</constraint>
<constraint loader="Mac OS X Mach-O" compilerSpecID="gcc">
<constraint primary="7" processor="x86" endian="little" size="32" />
<constraint primary="16777223" processor="x86" endian="little" size="64" />
</constraint>
<constraint loader="DYLD Cache" compilerSpecID="gcc">
<constraint primary="x86_64" processor="x86" endian="little" size="64" />
</constraint>
<constraint loader="Common Object File Format (COFF)" compilerSpecID="gcc">
<constraint primary="332" processor="x86" endian="little" size="32" />
<constraint primary="-31132" processor="x86" endian="little" size="64" />
</constraint>
<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="windows">
<constraint primary="332" processor="x86" endian="little" size="32" />
<constraint primary="-31132" processor="x86" endian="little" size="64" />
</constraint>
<constraint loader="Assembler Output (AOUT)" compilerSpecID="gcc">
<constraint primary="134" processor="x86" endian="little" size="32" />
</constraint>
<constraint loader="Relocatable Object Module Format (OMF)">
<constraint compilerSpecID="windows">
<constraint primary="32bit" processor="x86" endian="little" size="32" />
</constraint>
<constraint compilerSpecID="default">
<constraint primary="16bit" processor="x86" endian="little" size="16" />
</constraint>
<constraint compilerSpecID="borlandcpp">
<constraint primary="32bit" secondary="borlandcpp" processor="x86" endian="little" size="32" />
<constraint primary="32bit" secondary="codegearcpp" processor="x86" endian="little" size="32" />
</constraint>
<constraint compilerSpecID="borlanddelphi">
<constraint primary="32bit" secondary="borlanddelphi" processor="x86" endian="little" size="32" />
</constraint>
</constraint>
</opinions>

121
src/icicle/data/Ghidra/Processors/x86/data/languages/x86.pspec Normal file
View File

@@ -0,0 +1,121 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="useOperandReferenceAnalyzerSwitchTables" value="true"/>
<property key="assemblyRating:x86:LE:32:default" value="GOLD"/>
</properties>
<programcounter register="EIP"/>
<incidentalcopy>
<register name="ST0"/>
<register name="ST1"/>
<register name="ST2"/>
<register name="ST3"/>
<register name="ST4"/>
<register name="ST5"/>
<register name="ST6"/>
<register name="ST7"/>
</incidentalcopy>
<context_data>
<context_set space="ram">
<set name="addrsize" val="1"/>
<set name="opsize" val="1"/>
</context_set>
<tracked_set space="ram">
<set name="DF" val="0"/>
</tracked_set>
</context_data>
<register_data>
<register name="DR0" group="DEBUG"/>
<register name="DR1" group="DEBUG"/>
<register name="DR2" group="DEBUG"/>
<register name="DR3" group="DEBUG"/>
<register name="DR4" group="DEBUG"/>
<register name="DR5" group="DEBUG"/>
<register name="DR6" group="DEBUG"/>
<register name="DR7" group="DEBUG"/>
<register name="CR0" group="CONTROL"/>
<register name="CR2" group="CONTROL"/>
<register name="CR3" group="CONTROL"/>
<register name="CR4" group="CONTROL"/>
<register name="ST0" group="ST"/>
<register name="ST1" group="ST"/>
<register name="ST2" group="ST"/>
<register name="ST3" group="ST"/>
<register name="ST4" group="ST"/>
<register name="ST5" group="ST"/>
<register name="ST6" group="ST"/>
<register name="ST7" group="ST"/>
<register name="FPUControlWord" group="FPU"/>
<register name="FPUStatusWord" group="FPU"/>
<register name="FPUTagWord" group="FPU"/>
<register name="FPUInstructionPointer" group="FPU"/>
<register name="FPULastInstructionOpcode" group="FPU"/>
<register name="FPUDataPointer" group="FPU"/>
<register name="MM0" group="MMX"/>
<register name="MM1" group="MMX"/>
<register name="MM2" group="MMX"/>
<register name="MM3" group="MMX"/>
<register name="MM4" group="MMX"/>
<register name="MM5" group="MMX"/>
<register name="MM6" group="MMX"/>
<register name="MM7" group="MMX"/>
<register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" vector_lane_sizes="1,2,4,8"/>
<register name="CF" group="FLAGS"/>
<register name="F1" group="FLAGS"/>
<register name="PF" group="FLAGS"/>
<register name="F3" group="FLAGS"/>
<register name="AF" group="FLAGS"/>
<register name="F5" group="FLAGS"/>
<register name="ZF" group="FLAGS"/>
<register name="SF" group="FLAGS"/>
<register name="TF" group="FLAGS"/>
<register name="IF" group="FLAGS"/>
<register name="DF" group="FLAGS"/>
<register name="OF" group="FLAGS"/>
<register name="IOPL" group="FLAGS"/>
<register name="NT" group="FLAGS"/>
<register name="F15" group="FLAGS"/>
<register name="RF" group="FLAGS"/>
<register name="VM" group="FLAGS"/>
<register name="AC" group="FLAGS"/>
<register name="VIF" group="FLAGS"/>
<register name="VIP" group="FLAGS"/>
<register name="ID" group="FLAGS"/>
<register name="eflags" group="FLAGS"/>
<register name="flags" group="FLAGS"/>
<register name="repneprefx" hidden="true"/>
<register name="segover" hidden="true"/>
</register_data>
</processor_spec>

19
src/icicle/data/Ghidra/Processors/x86/data/languages/x86.slaspec Normal file
View File

@@ -0,0 +1,19 @@
@include "ia.sinc"
@include "lockable.sinc"
with : lockprefx=0 {
@include "avx.sinc"
@include "avx_manual.sinc"
@include "avx2.sinc"
@include "avx2_manual.sinc"
@include "adx.sinc"
@include "clwb.sinc"
@include "pclmulqdq.sinc"
@include "mpx.sinc"
@include "lzcnt.sinc"
@include "bmi1.sinc"
@include "bmi2.sinc"
@include "sha.sinc"
@include "smx.sinc"
@include "cet.sinc"
@include "rdrand.sinc"
}

150
src/icicle/data/Ghidra/Processors/x86/data/languages/x86borland.cspec Normal file
View File

@@ -0,0 +1,150 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="10" /> <!-- aligned-length=12 -->
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="ESP" space="ram"/>
<default_proto>
<prototype name="__fastcall" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EDX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="ECX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
</killedbycall>
</prototype>
</default_proto>
<prototype name="__stdcall" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="4"/>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
<register name="DF"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
</killedbycall>
<likelytrash>
<register name="ECX"/>
</likelytrash>
</prototype>
<prototype name="__cdecl" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="4"/>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
<register name="DF"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
</killedbycall>
<likelytrash>
<register name="ECX"/>
</likelytrash>
</prototype>
<prototype name="__thiscall" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
</killedbycall>
<likelytrash>
<register name="EAX"/>
</likelytrash>
</prototype>
<resolveprototype name="__stdcall/__fastcall">
<model name="__stdcall"/> <!-- The default case -->
<model name="__fastcall"/>
</resolveprototype>
<eval_current_prototype name="__stdcall/__fastcall"/>
</compiler_spec>

99
src/icicle/data/Ghidra/Processors/x86/data/languages/x86delphi.cspec Normal file
View File

@@ -0,0 +1,99 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="ram"/>
</global>
<stackpointer register="ESP" space="ram"/>
<default_proto>
<prototype name="__register" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EDX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="ECX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
</killedbycall>
</prototype>
</default_proto>
<!--there is also a "pascal" calling convention, which is the same as stdcall except that arguments are pushed left-to-right-->
<prototype name="__stdcall" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="4"/>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
<register name="DF"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
</killedbycall>
<likelytrash>
<register name="ECX"/>
</likelytrash>
</prototype>
<prototype name="__cdecl" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="4"/>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
<register name="DF"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
</killedbycall>
<likelytrash>
<register name="ECX"/>
</likelytrash>
</prototype>
</compiler_spec>

377
src/icicle/data/Ghidra/Processors/x86/data/languages/x86gcc.cspec Normal file
View File

@@ -0,0 +1,377 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="10" /> <!-- aligned-length=12 -->
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
<entry size="16" alignment="16" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
<range space="OTHER"/>
</global>
<stackpointer register="ESP" space="ram"/>
<returnaddress>
<varnode space="stack" offset="0" size="4"/>
</returnaddress>
<default_proto>
<prototype name="__cdecl" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="EAX"/>
</likelytrash>
</prototype>
</default_proto>
<prototype name="__cdeclf" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="10">
<register name="ST0"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
</killedbycall>
<likelytrash>
<register name="EAX"/>
</likelytrash>
</prototype>
<prototype name="__thiscall" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="EAX"/>
</likelytrash>
</prototype>
<prototype name="__regparm3" extrapop="4" stackshift="4"> <!-- Used particularly by linux kernel -->
<input>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EDX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="ECX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="EAX"/>
</likelytrash>
</prototype>
<prototype name="__regparm2" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EDX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="EAX"/>
</likelytrash>
</prototype>
<prototype name="__regparm1" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="EAX"/>
</likelytrash>
</prototype>
<prototype name="syscall" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="4">
<register name="EBX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="ECX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EDX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="ESI"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EDI"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EBP"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<register name="EBX"/>
<register name="ECX"/>
<register name="EDX"/>
<register name="EBP"/>
<register name="EDI"/>
<register name="ESI"/>
<register name="ESP"/>
<register name="DF"/>
</unaffected>
<killedbycall>
<register name="EAX"/>
</killedbycall>
</prototype>
<prototype name="processEntry" extrapop="0" stackshift="0">
<input pointermax="4">
<pentry minsize="1" maxsize="4">
<register name="EDX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
</output>
<unaffected>
<register name="ESP"/>
</unaffected>
<!-- Functions with this prototype don't have a return address. But, if we don't specify one, this prototype will
use the default, which is to have the return address on the stack. That conflicts with how this prototype actually
uses the stack, so we set a fake return address at a EBP, which is unspecified at process entry -->
<returnaddress>
<register name="EBP"/>
</returnaddress>
</prototype>
<resolveprototype name="__cdecl/__regparm">
<model name="__cdecl"/> <!-- The default case -->
<model name="__regparm3"/>
<model name="__regparm2"/>
<model name="__regparm1"/>
</resolveprototype>
<eval_current_prototype name="__cdecl/__regparm"/>
<callfixup name="get_pc_thunk_ax">
<target name="__i686.get_pc_thunk.ax"/>
<target name="__x86.get_pc_thunk.ax"/>
<pcode>
<body><![CDATA[
EAX = * ESP;
ESP = ESP + 4;
]]></body>
</pcode>
</callfixup>
<callfixup name="get_pc_thunk_bx">
<target name="__i686.get_pc_thunk.bx"/>
<target name="__x86.get_pc_thunk.bx"/>
<pcode>
<body><![CDATA[
EBX = * ESP;
ESP = ESP + 4;
]]></body>
</pcode>
</callfixup>
<callfixup name="get_pc_thunk_cx">
<target name="__i686.get_pc_thunk.cx"/>
<target name="__x86.get_pc_thunk.cx"/>
<pcode>
<body><![CDATA[
ECX = * ESP;
ESP = ESP + 4;
]]></body>
</pcode>
</callfixup>
<callfixup name="get_pc_thunk_dx">
<target name="__i686.get_pc_thunk.dx"/>
<target name="__x86.get_pc_thunk.dx"/>
<pcode>
<body><![CDATA[
EDX = * ESP;
ESP = ESP + 4;
]]></body>
</pcode>
</callfixup>
<callfixup name="get_pc_thunk_si">
<target name="__i686.get_pc_thunk.si"/>
<target name="__x86.get_pc_thunk.si"/>
<pcode>
<body><![CDATA[
ESI = * ESP;
ESP = ESP + 4;
]]></body>
</pcode>
</callfixup>
</compiler_spec>

380
src/icicle/data/Ghidra/Processors/x86/data/languages/x86win.cspec Normal file
View File

@@ -0,0 +1,380 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" /> <!-- no maximum alignment -->
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
<bitfield_packing>
<use_MS_convention value="true"/>
</bitfield_packing>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="ESP" space="ram"/>
<returnaddress>
<varnode space="stack" offset="0" size="4"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="4"/>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
<register name="DF"/>
<register name="FS_OFFSET"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="ECX"/>
</likelytrash>
</prototype>
</default_proto>
<prototype name="__cdecl" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="4"/>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
<register name="DF"/>
<register name="FS_OFFSET"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="ECX"/>
</likelytrash>
</prototype>
<prototype name="__fastcall" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="4">
<register name="ECX"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EDX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="4"/>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
<register name="DF"/>
<register name="FS_OFFSET"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="ECX"/>
</likelytrash>
</prototype>
<prototype name="__thiscall" extrapop="unknown" stackshift="4">
<input thisbeforeretpointer="true">
<pentry minsize="1" maxsize="4">
<register name="ECX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="4" maxsize="10" metatype="float" extension="float">
<register name="ST0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="EAX"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="EDX" piece2="EAX"/>
</pentry>
</output>
<unaffected>
<varnode space="ram" offset="0" size="4"/>
<register name="ESP"/>
<register name="EBP"/>
<register name="ESI"/>
<register name="EDI"/>
<register name="EBX"/>
<register name="DF"/>
<register name="FS_OFFSET"/>
</unaffected>
<killedbycall>
<register name="ECX"/>
<register name="EDX"/>
<register name="ST0"/>
<register name="ST1"/>
</killedbycall>
<likelytrash>
<register name="ECX"/>
</likelytrash>
</prototype>
<resolveprototype name="__fastcall/__thiscall/__stdcall">
<model name="__stdcall"/> <!-- The default case -->
<model name="__fastcall"/>
<model name="__thiscall"/>
</resolveprototype>
<eval_current_prototype name="__fastcall/__thiscall/__stdcall"/>
<!-- Injections for various compiler helper functions -->
<callfixup name="EH_prolog">
<target name="__EH_prolog"/>
<target name="_EH_prolog"/>
<target name="thunk_EH_prolog"/>
<pcode>
<body><![CDATA[
ESP = ESP - 4;
*:4 ESP = -1;
ESP = ESP - 4;
* ESP = EAX;
EAX = * FS_OFFSET;
ESP = ESP - 4;
* ESP = EAX;
* FS_OFFSET = ESP;
tmp = ESP + 12;
* tmp = EBP;
EBP = tmp;
]]></body>
</pcode>
</callfixup>
<callfixup name="EH_prolog3">
<target name="_EH_prolog3"/>
<target name="__EH_prolog3"/>
<target name="EH_prolog3_GS"/>
<target name="_EH_prolog3_GS"/>
<target name="__EH_prolog3_GS"/>
<target name="EH_prolog3_catch"/>
<target name="_EH_prolog3_catch"/>
<target name="__EH_prolog3_catch"/>
<target name="EH_prolog3_catch_GS"/>
<target name="_EH_prolog3_catch_GS"/>
<target name="__EH_prolog3_catch_GS"/>
<target name="EH_prolog3_catch"/>
<target name="_EH_prolog3_catch"/>
<target name="__EH_prolog3_catch"/>
<target name="EH_prolog3_catch_GS"/>
<target name="_EH_prolog3_catch_GS"/>
<target name="__EH_prolog3_catch_GS"/>
<pcode>
<body><![CDATA[
EBP = ESP + 4;
tmp = * EBP;
ESP = ESP - tmp;
ESP = ESP - 24;
]]></body>
</pcode>
</callfixup>
<callfixup name="EH_epilog3">
<target name="_EH_epilog3"/>
<target name="__EH_epilog3"/>
<target name="EH_epilog3_GS"/>
<target name="_EH_epilog3_GS"/>
<target name="__EH_epilog3_GS"/>
<target name="EH_epilog3_catch"/>
<target name="_EH_epilog3_catch"/>
<target name="__EH_epilog3_catch"/>
<target name="EH_epilog3_catch_GS"/>
<target name="_EH_epilog3_catch_GS"/>
<target name="FID_conflict:__EH_epilog3_GS"/>
<target name="FID_conflict:__EH_epilog3_catch"/>
<target name="FID_conflict:__EH_epilog3_catch_GS"/>
<target name="SEH_epilog"/>
<target name="_SEH_epilog"/>
<target name="__SEH_epilog"/>
<target name="SEH_epilog4"/>
<target name="_SEH_epilog4"/>
<target name="__SEH_epilog4"/>
<target name="SEH_epilog4_GS"/>
<target name="_SEH_epilog4_GS"/>
<target name="__SEH_epilog4_GS"/>
<target name="FID_conflict:__SEH_epilog4_GS"/>
<pcode>
<body><![CDATA[
ESP = EBP;
EBP = * ESP;
ESP = ESP + 4;
]]></body>
</pcode>
</callfixup>
<!-- Not sure if these are ever used, and how they affect the stack
<callfixup name="EH_prolog3_align">
<target name="_EH_prolog3_align"/>
<target name="__EH_prolog3_align"/>
<target name="EH_prolog3_GS_align"/>
<target name="_EH_prolog3_GS_align"/>
<target name="__EH_prolog3_GS_align"/>
<target name="EH_prolog3_catch_align"/>
<target name="_EH_prolog3_catch_align"/>
<target name="__EH_prolog3_catch_align"/>
<target name="EH_prolog3_catch_GS_align"/>
<target name="_EH_prolog3_catch_GS_align"/>
<target name="__EH_prolog3_catch_GS_align"/>
<pcode>
<body><![CDATA[
EBP = ESP + 4;
tmp = * EBP;
ESP = ESP - tmp;
ESP = ESP - 24;
]]></body>
</pcode>
</callfixup>
<callfixup name="EH_epilog3_align">
<target name="_EH_epilog3_align"/>
<target name="__EH_epilog3_align"/>
<target name="EH_epilog3_GS_align"/>
<target name="_EH_epilog3_GS_align"/>
<target name="__EH_epilog3_GS_align"/>
<pcode>
<body><![CDATA[
ESP = EBP;
EBP = * ESP;
ESP = ESP - 4;
]]></body>
</pcode>
</callfixup>
-->
<callfixup name="alloca_probe">
<target name="__alloca_probe"/>
<target name="__alloca_probe_8"/>
<target name="__alloca_probe_16"/>
<target name="__chkstk"/>
<pcode>
<body><![CDATA[
ESP = ESP + 4 - EAX;
]]></body>
</pcode>
</callfixup>
<callfixup name="SEH_prolog">
<target name="_SEH_prolog"/>
<target name="__SEH_prolog"/>
<pcode>
<body><![CDATA[
newframetmp = ESP + 8;
localsizetmp:4 = * newframetmp;
ESP = ESP - localsizetmp;
ESP = ESP - 20;
* newframetmp = EBP;
EBP = newframetmp;
*ESP = EDI;
*(ESP+4) = ESI;
*(ESP+8) = EBX;
]]></body>
</pcode>
</callfixup>
<callfixup name="SEH_prolog4">
<target name="_SEH_prolog4"/>
<target name="__SEH_prolog4"/>
<target name="SEH_prolog4_GS"/>
<target name="_SEH_prolog4_GS"/>
<target name="__SEH_prolog4_GS"/>
<pcode>
<body><![CDATA[
newframetmp = ESP + 8;
localsizetmp:4 = * newframetmp;
ESP = ESP - localsizetmp;
ESP = ESP - 24;
* newframetmp = EBP;
EBP = newframetmp;
*(ESP+4) = EDI;
*(ESP+8) = ESI;
*(ESP+12) = EBX;
]]></body>
</pcode>
</callfixup>
</compiler_spec>

44
src/icicle/src/lib.rs
View File

@@ -38,8 +38,8 @@ pub fn icicle_stop(ptr: *mut c_void) {
type RawFunction = extern "C" fn(*mut c_void);
type PtrFunction = extern "C" fn(*mut c_void, u64);
type DataFunction = extern "C" fn(*mut c_void, *const c_void, usize);
type MmioReadFunction = extern "C" fn(*mut c_void, u64, usize, *mut c_void);
type MmioWriteFunction = extern "C" fn(*mut c_void, u64, usize, *const c_void);
type MmioReadFunction = extern "C" fn(*mut c_void, u64, *mut c_void, usize);
type MmioWriteFunction = extern "C" fn(*mut c_void, u64, *const c_void, usize);
type ViolationFunction = extern "C" fn(*mut c_void, u64, u8, i32) -> i32;
#[unsafe(no_mangle)]
@@ -57,12 +57,12 @@ pub fn icicle_map_mmio(
let read_wrapper = Box::new(move |addr: u64, data: &mut [u8]| {
let raw_pointer: *mut u8 = data.as_mut_ptr();
read_cb(read_data, addr, data.len(), raw_pointer as *mut c_void);
read_cb(read_data, addr, raw_pointer as *mut c_void, data.len());
});
let write_wrapper = Box::new(move |addr: u64, data: &[u8]| {
let raw_pointer: *const u8 = data.as_ptr();
write_cb(write_data, addr, data.len(), raw_pointer as *const c_void);
write_cb(write_data, addr, raw_pointer as *const c_void, data.len());
});
let res = emulator.map_mmio(address, length, read_wrapper, write_wrapper);
@@ -104,6 +104,14 @@ pub fn icicle_write_memory(
data: *const c_void,
size: usize,
) -> i32 {
if size == 0 {
return 1;
}
if data.is_null() {
return 0;
}
unsafe {
let emulator = &mut *(ptr as *mut IcicleEmulator);
let u8_slice = std::slice::from_raw_parts(data as *const u8, size);
@@ -127,6 +135,10 @@ pub fn icicle_save_registers(ptr: *mut c_void, accessor: DataFunction, accessor_
#[unsafe(no_mangle)]
pub fn icicle_restore_registers(ptr: *mut c_void, data: *const c_void, size: usize) {
if size == 0 || data.is_null() {
return;
}
unsafe {
let emulator = &mut *(ptr as *mut IcicleEmulator);
let u8_slice = std::slice::from_raw_parts(data as *const u8, size);
@@ -136,6 +148,14 @@ pub fn icicle_restore_registers(ptr: *mut c_void, data: *const c_void, size: usi
#[unsafe(no_mangle)]
pub fn icicle_read_memory(ptr: *mut c_void, address: u64, data: *mut c_void, size: usize) -> i32 {
if size == 0 {
return 1;
}
if data.is_null() {
return 0;
}
unsafe {
let emulator = &mut *(ptr as *mut IcicleEmulator);
let u8_slice = std::slice::from_raw_parts_mut(data as *mut u8, size);
@@ -192,6 +212,14 @@ pub fn icicle_read_register(
data: *mut c_void,
size: usize,
) -> usize {
if size == 0 {
return 1;
}
if data.is_null() {
return 0;
}
unsafe {
let emulator = &mut *(ptr as *mut IcicleEmulator);
let u8_slice = std::slice::from_raw_parts_mut(data as *mut u8, size);
@@ -206,6 +234,14 @@ pub fn icicle_write_register(
data: *const c_void,
size: usize,
) -> usize {
if size == 0 {
return 1;
}
if data.is_null() {
return 0;
}
unsafe {
let emulator = &mut *(ptr as *mut IcicleEmulator);
let u8_slice = std::slice::from_raw_parts(data as *const u8, size);

32
src/unicorn-emulator/unicorn_x64_emulator.cpp
View File

@@ -243,6 +243,14 @@ namespace unicorn
return block;
}
void assert_64bit_limit(const size_t size)
{
if (size > sizeof(uint64_t))
{
throw std::runtime_error("Exceeded uint64_t size limit");
}
}
class unicorn_x64_emulator : public x64_emulator
{
public:
@@ -370,13 +378,23 @@ namespace unicorn
void map_mmio(const uint64_t address, const size_t size, mmio_read_callback read_cb,
mmio_write_callback write_cb) override
{
mmio_callbacks cb{.read = mmio_callbacks::read_wrapper(
[c = std::move(read_cb)](uc_engine*, const uint64_t addr, const uint32_t s) {
return c(addr, s);
}),
.write = mmio_callbacks::write_wrapper(
[c = std::move(write_cb)](uc_engine*, const uint64_t addr, const uint32_t s,
const uint64_t value) { c(addr, s, value); })};
auto read_wrapper = [c = std::move(read_cb)](uc_engine*, const uint64_t addr, const uint32_t s) {
assert_64bit_limit(s);
uint64_t value{};
c(addr, &value, s);
return value;
};
auto write_wrapper = [c = std::move(write_cb)](uc_engine*, const uint64_t addr, const uint32_t s,
const uint64_t value) {
assert_64bit_limit(s);
c(addr, &value, s);
};
mmio_callbacks cb{
.read = mmio_callbacks::read_wrapper(std::move(read_wrapper)),
.write = mmio_callbacks::write_wrapper(std::move(write_wrapper)),
};
uce(uc_mmio_map(*this, address, size, cb.read.get_c_function(), cb.read.get_user_data(),
cb.write.get_c_function(), cb.write.get_user_data()));

25
src/windows-emulator/kusd_mmio.cpp
View File

@@ -83,13 +83,13 @@ namespace
namespace utils
{
inline void serialize(buffer_serializer& buffer, const KUSER_SHARED_DATA64& kusd)
static void serialize(buffer_serializer& buffer, const KUSER_SHARED_DATA64& kusd)
{
static_assert(KUSD_SIZE == sizeof(kusd));
buffer.write(&kusd, KUSD_SIZE);
}
inline void deserialize(buffer_deserializer& buffer, KUSER_SHARED_DATA64& kusd)
static void deserialize(buffer_deserializer& buffer, KUSER_SHARED_DATA64& kusd)
{
buffer.read(&kusd, KUSD_SIZE);
}
@@ -130,30 +130,21 @@ void kusd_mmio::deserialize(utils::buffer_deserializer& buffer)
this->register_mmio();
}
uint64_t kusd_mmio::read(const uint64_t addr, const size_t size)
void kusd_mmio::read(const uint64_t addr, void* data, const size_t size)
{
uint64_t result{};
this->update();
if (addr >= KUSD_SIZE)
{
return result;
return;
}
const auto end = addr + size;
const auto valid_end = std::min(end, static_cast<uint64_t>(KUSD_SIZE));
const auto real_size = valid_end - addr;
if (real_size > sizeof(result))
{
return result;
}
const auto* kusd_buffer = reinterpret_cast<uint8_t*>(&this->kusd_);
memcpy(&result, kusd_buffer + addr, real_size);
return result;
memcpy(data, kusd_buffer + addr, real_size);
}
uint64_t kusd_mmio::address()
@@ -178,8 +169,10 @@ void kusd_mmio::register_mmio()
this->memory_->allocate_mmio(
KUSD_ADDRESS, KUSD_BUFFER_SIZE,
[this](const uint64_t addr, const size_t size) { return this->read(addr, size); },
[](const uint64_t, const size_t, const uint64_t) {
[this](const uint64_t addr, void* data, const size_t size) {
this->read(addr, data, size); //
},
[](const uint64_t, const void*, const size_t) {
// Writing not supported!
});
}

2
src/windows-emulator/kusd_mmio.hpp
View File

@@ -48,7 +48,7 @@ class kusd_mmio
KUSER_SHARED_DATA64 kusd_{};
uint64_t read(uint64_t addr, size_t size);
void read(uint64_t addr, void* data, size_t size);
void update();

4
src/windows-emulator/memory_manager.hpp
View File

@@ -20,8 +20,8 @@ struct region_info : basic_memory_region
bool is_committed{};
};
using mmio_read_callback = std::function<uint64_t(uint64_t addr, size_t size)>;
using mmio_write_callback = std::function<void(uint64_t addr, size_t size, uint64_t data)>;
using mmio_read_callback = std::function<void(uint64_t addr, void* data, size_t size)>;
using mmio_write_callback = std::function<void(uint64_t addr, const void* data, size_t size)>;
class memory_manager : public memory_interface
{

8
src/windows-emulator/windows_emulator.cpp
View File

@@ -210,6 +210,14 @@ namespace
std::unique_ptr<x64_emulator> create_default_x64_emulator()
{
#if MOMO_ENABLE_RUST_CODE
const auto* env = getenv("EMULATOR_ICICLE");
if (env && (env == "1"sv || env == "true"sv))
{
return icicle::create_x64_emulator();
}
#endif
return unicorn::create_x64_emulator();
}