mirror of
https://github.com/momo5502/emulator.git
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Extract registers
This commit is contained in:
momo5502
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,8 @@
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mod icicle;
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mod registers;
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use icicle::{IcicleEmulator, X64Register};
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use icicle::IcicleEmulator;
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use registers::X64Register;
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use std::os::raw::c_void;
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fn to_cbool(value: bool) -> i32 {
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949
src/icicle/src/registers.rs
Normal file
949
src/icicle/src/registers.rs
Normal file
@@ -0,0 +1,949 @@
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#[repr(i32)]
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#[derive(PartialEq)]
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pub enum X64Register {
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Invalid = 0,
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Ah,
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Al,
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Ax,
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Bh,
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Bl,
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Bp,
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Bpl,
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Bx,
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Ch,
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Cl,
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Cs,
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Cx,
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Dh,
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Di,
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Dil,
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Dl,
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Ds,
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Dx,
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Eax,
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Ebp,
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Ebx,
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Ecx,
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Edi,
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Edx,
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Eflags,
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Eip,
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Es = 26 + 2,
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Esi,
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Esp,
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Fpsw,
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Fs,
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Gs,
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Ip,
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Rax,
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Rbp,
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Rbx,
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Rcx,
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Rdi,
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Rdx,
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Rip,
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Rsi = 41 + 2,
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Rsp,
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Si,
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Sil,
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Sp,
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Spl,
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Ss,
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Cr0,
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Cr1,
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Cr2,
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Cr3,
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Cr4,
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Cr8 = 54 + 4,
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Dr0 = 58 + 8,
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Dr1,
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Dr2,
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Dr3,
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Dr4,
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Dr5,
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Dr6,
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Dr7,
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Fp0 = 73 + 9,
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Fp1,
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Fp2,
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Fp3,
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Fp4,
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Fp5,
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Fp6,
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Fp7,
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K0,
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K1,
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K2,
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K3,
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K4,
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K5,
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K6,
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K7,
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Mm0,
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Mm1,
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Mm2,
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Mm3,
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Mm4,
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Mm5,
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Mm6,
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Mm7,
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R8,
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R9,
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R10,
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R11,
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R12,
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R13,
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R14,
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R15,
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St0,
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St1,
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St2,
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St3,
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St4,
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St5,
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St6,
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St7,
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Xmm0,
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Xmm1,
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Xmm2,
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Xmm3,
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Xmm4,
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Xmm5,
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Xmm6,
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Xmm7,
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Xmm8,
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Xmm9,
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Xmm10,
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Xmm11,
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Xmm12,
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Xmm13,
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Xmm14,
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Xmm15,
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Xmm16,
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Xmm17,
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Xmm18,
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Xmm19,
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Xmm20,
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Xmm21,
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Xmm22,
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Xmm23,
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Xmm24,
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Xmm25,
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Xmm26,
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Xmm27,
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Xmm28,
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Xmm29,
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Xmm30,
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Xmm31,
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Ymm0,
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Ymm1,
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Ymm2,
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Ymm3,
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Ymm4,
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Ymm5,
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Ymm6,
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Ymm7,
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Ymm8,
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Ymm9,
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Ymm10,
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Ymm11,
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Ymm12,
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Ymm13,
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Ymm14,
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Ymm15,
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Ymm16,
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Ymm17,
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Ymm18,
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Ymm19,
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Ymm20,
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Ymm21,
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Ymm22,
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Ymm23,
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Ymm24,
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Ymm25,
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Ymm26,
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Ymm27,
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Ymm28,
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Ymm29,
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Ymm30,
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Ymm31,
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Zmm0,
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Zmm1,
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Zmm2,
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Zmm3,
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Zmm4,
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Zmm5,
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Zmm6,
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Zmm7,
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Zmm8,
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Zmm9,
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Zmm10,
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Zmm11,
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Zmm12,
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Zmm13,
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Zmm14,
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Zmm15,
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Zmm16,
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Zmm17,
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Zmm18,
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Zmm19,
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Zmm20,
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Zmm21,
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Zmm22,
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Zmm23,
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Zmm24,
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Zmm25,
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Zmm26,
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Zmm27,
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Zmm28,
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Zmm29,
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Zmm30,
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Zmm31,
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R8b,
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R9b,
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R10b,
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R11b,
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R12b,
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R13b,
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R14b,
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R15b,
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R8d,
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R9d,
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R10d,
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R11d,
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R12d,
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R13d,
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R14d,
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R15d,
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R8w,
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R9w,
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R10w,
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R11w,
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R12w,
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R13w,
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R14w,
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R15w,
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Idtr,
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Gdtr,
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Ldtr,
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Tr,
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Fpcw,
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Fptag,
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Msr,
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Mxcsr,
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FsBase,
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GsBase,
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Flags,
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Rflags,
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Fip,
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Fcs,
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Fdp,
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Fds,
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Fop,
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End, // Must be last
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}
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#[derive(Clone)]
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pub(crate) struct X64RegisterNodes {
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rax: pcode::VarNode,
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rbx: pcode::VarNode,
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rcx: pcode::VarNode,
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rdx: pcode::VarNode,
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rsi: pcode::VarNode,
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rdi: pcode::VarNode,
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rbp: pcode::VarNode,
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rsp: pcode::VarNode,
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r8: pcode::VarNode,
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r9: pcode::VarNode,
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r10: pcode::VarNode,
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r11: pcode::VarNode,
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r12: pcode::VarNode,
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r13: pcode::VarNode,
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r14: pcode::VarNode,
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r15: pcode::VarNode,
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rip: pcode::VarNode,
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eflags: pcode::VarNode,
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cs: pcode::VarNode,
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ds: pcode::VarNode,
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es: pcode::VarNode,
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fs: pcode::VarNode,
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gs: pcode::VarNode,
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ss: pcode::VarNode,
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ah: pcode::VarNode,
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al: pcode::VarNode,
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ax: pcode::VarNode,
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bh: pcode::VarNode,
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bl: pcode::VarNode,
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bpl: pcode::VarNode,
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ch: pcode::VarNode,
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cl: pcode::VarNode,
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cx: pcode::VarNode,
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dh: pcode::VarNode,
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dil: pcode::VarNode,
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dl: pcode::VarNode,
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dx: pcode::VarNode,
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eax: pcode::VarNode,
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ebp: pcode::VarNode,
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ebx: pcode::VarNode,
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ecx: pcode::VarNode,
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edi: pcode::VarNode,
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edx: pcode::VarNode,
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esi: pcode::VarNode,
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esp: pcode::VarNode,
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fpsw: pcode::VarNode,
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gdtr: pcode::VarNode,
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idtr: pcode::VarNode,
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ldtr: pcode::VarNode,
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tr: pcode::VarNode,
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cr0: pcode::VarNode,
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cr1: pcode::VarNode,
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cr2: pcode::VarNode,
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cr3: pcode::VarNode,
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cr4: pcode::VarNode,
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cr8: pcode::VarNode,
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dr0: pcode::VarNode,
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dr1: pcode::VarNode,
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dr2: pcode::VarNode,
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dr3: pcode::VarNode,
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dr4: pcode::VarNode,
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dr5: pcode::VarNode,
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dr6: pcode::VarNode,
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dr7: pcode::VarNode,
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fp0: pcode::VarNode,
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fp1: pcode::VarNode,
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fp2: pcode::VarNode,
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fp3: pcode::VarNode,
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fp4: pcode::VarNode,
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fp5: pcode::VarNode,
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fp6: pcode::VarNode,
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fp7: pcode::VarNode,
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/*k0: pcode::VarNode,
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k1: pcode::VarNode,
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k2: pcode::VarNode,
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k3: pcode::VarNode,
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k4: pcode::VarNode,
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k5: pcode::VarNode,
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k6: pcode::VarNode,
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k7: pcode::VarNode,*/
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mm0: pcode::VarNode,
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mm1: pcode::VarNode,
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mm2: pcode::VarNode,
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mm3: pcode::VarNode,
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mm4: pcode::VarNode,
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mm5: pcode::VarNode,
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mm6: pcode::VarNode,
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mm7: pcode::VarNode,
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st0: pcode::VarNode,
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st1: pcode::VarNode,
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st2: pcode::VarNode,
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st3: pcode::VarNode,
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st4: pcode::VarNode,
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st5: pcode::VarNode,
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st6: pcode::VarNode,
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st7: pcode::VarNode,
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xmm0: pcode::VarNode,
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xmm1: pcode::VarNode,
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xmm2: pcode::VarNode,
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xmm3: pcode::VarNode,
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xmm4: pcode::VarNode,
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xmm5: pcode::VarNode,
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xmm6: pcode::VarNode,
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xmm7: pcode::VarNode,
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xmm8: pcode::VarNode,
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xmm9: pcode::VarNode,
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xmm10: pcode::VarNode,
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xmm11: pcode::VarNode,
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xmm12: pcode::VarNode,
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xmm13: pcode::VarNode,
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xmm14: pcode::VarNode,
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xmm15: pcode::VarNode,
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/*xmm16: pcode::VarNode,
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xmm17: pcode::VarNode,
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xmm18: pcode::VarNode,
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xmm19: pcode::VarNode,
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xmm20: pcode::VarNode,
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xmm21: pcode::VarNode,
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xmm22: pcode::VarNode,
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xmm23: pcode::VarNode,
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xmm24: pcode::VarNode,
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xmm25: pcode::VarNode,
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xmm26: pcode::VarNode,
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xmm27: pcode::VarNode,
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xmm28: pcode::VarNode,
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xmm29: pcode::VarNode,
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xmm30: pcode::VarNode,
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||||
xmm31: pcode::VarNode,*/
|
||||
ymm0: pcode::VarNode,
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||||
ymm1: pcode::VarNode,
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||||
ymm2: pcode::VarNode,
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||||
ymm3: pcode::VarNode,
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||||
ymm4: pcode::VarNode,
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||||
ymm5: pcode::VarNode,
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||||
ymm6: pcode::VarNode,
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||||
ymm7: pcode::VarNode,
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||||
ymm8: pcode::VarNode,
|
||||
ymm9: pcode::VarNode,
|
||||
ymm10: pcode::VarNode,
|
||||
ymm11: pcode::VarNode,
|
||||
ymm12: pcode::VarNode,
|
||||
ymm13: pcode::VarNode,
|
||||
ymm14: pcode::VarNode,
|
||||
ymm15: pcode::VarNode,
|
||||
/*ymm16: pcode::VarNode,
|
||||
ymm17: pcode::VarNode,
|
||||
ymm18: pcode::VarNode,
|
||||
ymm19: pcode::VarNode,
|
||||
ymm20: pcode::VarNode,
|
||||
ymm21: pcode::VarNode,
|
||||
ymm22: pcode::VarNode,
|
||||
ymm23: pcode::VarNode,
|
||||
ymm24: pcode::VarNode,
|
||||
ymm25: pcode::VarNode,
|
||||
ymm26: pcode::VarNode,
|
||||
ymm27: pcode::VarNode,
|
||||
ymm28: pcode::VarNode,
|
||||
ymm29: pcode::VarNode,
|
||||
ymm30: pcode::VarNode,
|
||||
ymm31: pcode::VarNode,*/
|
||||
/*zmm0: pcode::VarNode,
|
||||
zmm1: pcode::VarNode,
|
||||
zmm2: pcode::VarNode,
|
||||
zmm3: pcode::VarNode,
|
||||
zmm4: pcode::VarNode,
|
||||
zmm5: pcode::VarNode,
|
||||
zmm6: pcode::VarNode,
|
||||
zmm7: pcode::VarNode,
|
||||
zmm8: pcode::VarNode,
|
||||
zmm9: pcode::VarNode,
|
||||
zmm10: pcode::VarNode,
|
||||
zmm11: pcode::VarNode,
|
||||
zmm12: pcode::VarNode,
|
||||
zmm13: pcode::VarNode,
|
||||
zmm14: pcode::VarNode,
|
||||
zmm15: pcode::VarNode,
|
||||
zmm16: pcode::VarNode,
|
||||
zmm17: pcode::VarNode,
|
||||
zmm18: pcode::VarNode,
|
||||
zmm19: pcode::VarNode,
|
||||
zmm20: pcode::VarNode,
|
||||
zmm21: pcode::VarNode,
|
||||
zmm22: pcode::VarNode,
|
||||
zmm23: pcode::VarNode,
|
||||
zmm24: pcode::VarNode,
|
||||
zmm25: pcode::VarNode,
|
||||
zmm26: pcode::VarNode,
|
||||
zmm27: pcode::VarNode,
|
||||
zmm28: pcode::VarNode,
|
||||
zmm29: pcode::VarNode,
|
||||
zmm30: pcode::VarNode,
|
||||
zmm31: pcode::VarNode,*/
|
||||
r8b: pcode::VarNode,
|
||||
r9b: pcode::VarNode,
|
||||
r10b: pcode::VarNode,
|
||||
r11b: pcode::VarNode,
|
||||
r12b: pcode::VarNode,
|
||||
r13b: pcode::VarNode,
|
||||
r14b: pcode::VarNode,
|
||||
r15b: pcode::VarNode,
|
||||
r8d: pcode::VarNode,
|
||||
r9d: pcode::VarNode,
|
||||
r10d: pcode::VarNode,
|
||||
r11d: pcode::VarNode,
|
||||
r12d: pcode::VarNode,
|
||||
r13d: pcode::VarNode,
|
||||
r14d: pcode::VarNode,
|
||||
r15d: pcode::VarNode,
|
||||
r8w: pcode::VarNode,
|
||||
r9w: pcode::VarNode,
|
||||
r10w: pcode::VarNode,
|
||||
r11w: pcode::VarNode,
|
||||
r12w: pcode::VarNode,
|
||||
r13w: pcode::VarNode,
|
||||
r14w: pcode::VarNode,
|
||||
r15w: pcode::VarNode,
|
||||
fpcw: pcode::VarNode,
|
||||
fptag: pcode::VarNode,
|
||||
//msr: pcode::VarNode,
|
||||
mxcsr: pcode::VarNode,
|
||||
fs_base: pcode::VarNode,
|
||||
gs_base: pcode::VarNode,
|
||||
flags: pcode::VarNode,
|
||||
rflags: pcode::VarNode,
|
||||
fip: pcode::VarNode,
|
||||
//fcs: pcode::VarNode,
|
||||
fdp: pcode::VarNode,
|
||||
//fds: pcode::VarNode,
|
||||
fop: pcode::VarNode,
|
||||
}
|
||||
|
||||
impl X64RegisterNodes {
|
||||
pub fn new(arch: &icicle_cpu::Arch) -> Self {
|
||||
let r = |name: &str| arch.sleigh.get_reg(name).unwrap().var;
|
||||
Self {
|
||||
rax: r("RAX"),
|
||||
rbx: r("RBX"),
|
||||
rcx: r("RCX"),
|
||||
rdx: r("RDX"),
|
||||
rsi: r("RSI"),
|
||||
rdi: r("RDI"),
|
||||
rbp: r("RBP"),
|
||||
rsp: r("RSP"),
|
||||
r8: r("R8"),
|
||||
r9: r("R9"),
|
||||
r10: r("R10"),
|
||||
r11: r("R11"),
|
||||
r12: r("R12"),
|
||||
r13: r("R13"),
|
||||
r14: r("R14"),
|
||||
r15: r("R15"),
|
||||
rip: r("RIP"),
|
||||
eflags: r("eflags"),
|
||||
cs: r("CS"),
|
||||
ds: r("DS"),
|
||||
es: r("ES"),
|
||||
fs: r("FS"),
|
||||
gs: r("GS"),
|
||||
ss: r("SS"),
|
||||
ah: r("AH"),
|
||||
al: r("AL"),
|
||||
ax: r("AX"),
|
||||
bh: r("BH"),
|
||||
bl: r("BL"),
|
||||
bpl: r("BPL"),
|
||||
ch: r("CH"),
|
||||
cl: r("CL"),
|
||||
cx: r("CX"),
|
||||
dh: r("DH"),
|
||||
dil: r("DIL"),
|
||||
dl: r("DL"),
|
||||
dx: r("DX"),
|
||||
eax: r("EAX"),
|
||||
ebp: r("EBP"),
|
||||
ebx: r("EBX"),
|
||||
ecx: r("ECX"),
|
||||
edi: r("EDI"),
|
||||
edx: r("EDX"),
|
||||
esi: r("ESI"),
|
||||
esp: r("ESP"),
|
||||
fpsw: r("FPUStatusWord"),
|
||||
gdtr: r("GDTR"),
|
||||
idtr: r("IDTR"),
|
||||
ldtr: r("LDTR"),
|
||||
tr: r("TR"),
|
||||
cr0: r("CR0"),
|
||||
cr1: r("CR1"),
|
||||
cr2: r("CR2"),
|
||||
cr3: r("CR3"),
|
||||
cr4: r("CR4"),
|
||||
cr8: r("CR8"),
|
||||
dr0: r("DR0"),
|
||||
dr1: r("DR1"),
|
||||
dr2: r("DR2"),
|
||||
dr3: r("DR3"),
|
||||
dr4: r("DR4"),
|
||||
dr5: r("DR5"),
|
||||
dr6: r("DR6"),
|
||||
dr7: r("DR7"),
|
||||
fp0: r("ST0"), // ??
|
||||
fp1: r("ST1"),
|
||||
fp2: r("ST2"),
|
||||
fp3: r("ST3"),
|
||||
fp4: r("ST4"),
|
||||
fp5: r("ST5"),
|
||||
fp6: r("ST6"),
|
||||
fp7: r("ST7"),
|
||||
/*k0: r("K0"),
|
||||
k1: r("K1"),
|
||||
k2: r("K2"),
|
||||
k3: r("K3"),
|
||||
k4: r("K4"),
|
||||
k5: r("K5"),
|
||||
k6: r("K6"),
|
||||
k7: r("K7"),*/
|
||||
mm0: r("MM0"),
|
||||
mm1: r("MM1"),
|
||||
mm2: r("MM2"),
|
||||
mm3: r("MM3"),
|
||||
mm4: r("MM4"),
|
||||
mm5: r("MM5"),
|
||||
mm6: r("MM6"),
|
||||
mm7: r("MM7"),
|
||||
st0: r("ST0"),
|
||||
st1: r("ST1"),
|
||||
st2: r("ST2"),
|
||||
st3: r("ST3"),
|
||||
st4: r("ST4"),
|
||||
st5: r("ST5"),
|
||||
st6: r("ST6"),
|
||||
st7: r("ST7"),
|
||||
xmm0: r("XMM0"),
|
||||
xmm1: r("XMM1"),
|
||||
xmm2: r("XMM2"),
|
||||
xmm3: r("XMM3"),
|
||||
xmm4: r("XMM4"),
|
||||
xmm5: r("XMM5"),
|
||||
xmm6: r("XMM6"),
|
||||
xmm7: r("XMM7"),
|
||||
xmm8: r("XMM8"),
|
||||
xmm9: r("XMM9"),
|
||||
xmm10: r("XMM10"),
|
||||
xmm11: r("XMM11"),
|
||||
xmm12: r("XMM12"),
|
||||
xmm13: r("XMM13"),
|
||||
xmm14: r("XMM14"),
|
||||
xmm15: r("XMM15"),
|
||||
/*xmm16: r("XMM16"),
|
||||
xmm17: r("XMM17"),
|
||||
xmm18: r("XMM18"),
|
||||
xmm19: r("XMM19"),
|
||||
xmm20: r("XMM20"),
|
||||
xmm21: r("XMM21"),
|
||||
xmm22: r("XMM22"),
|
||||
xmm23: r("XMM23"),
|
||||
xmm24: r("XMM24"),
|
||||
xmm25: r("XMM25"),
|
||||
xmm26: r("XMM26"),
|
||||
xmm27: r("XMM27"),
|
||||
xmm28: r("XMM28"),
|
||||
xmm29: r("XMM29"),
|
||||
xmm30: r("XMM30"),
|
||||
xmm31: r("XMM31"),*/
|
||||
ymm0: r("YMM0"),
|
||||
ymm1: r("YMM1"),
|
||||
ymm2: r("YMM2"),
|
||||
ymm3: r("YMM3"),
|
||||
ymm4: r("YMM4"),
|
||||
ymm5: r("YMM5"),
|
||||
ymm6: r("YMM6"),
|
||||
ymm7: r("YMM7"),
|
||||
ymm8: r("YMM8"),
|
||||
ymm9: r("YMM9"),
|
||||
ymm10: r("YMM10"),
|
||||
ymm11: r("YMM11"),
|
||||
ymm12: r("YMM12"),
|
||||
ymm13: r("YMM13"),
|
||||
ymm14: r("YMM14"),
|
||||
ymm15: r("YMM15"),
|
||||
/*ymm16: r("YMM16"),
|
||||
ymm17: r("YMM17"),
|
||||
ymm18: r("YMM18"),
|
||||
ymm19: r("YMM19"),
|
||||
ymm20: r("YMM20"),
|
||||
ymm21: r("YMM21"),
|
||||
ymm22: r("YMM22"),
|
||||
ymm23: r("YMM23"),
|
||||
ymm24: r("YMM24"),
|
||||
ymm25: r("YMM25"),
|
||||
ymm26: r("YMM26"),
|
||||
ymm27: r("YMM27"),
|
||||
ymm28: r("YMM28"),
|
||||
ymm29: r("YMM29"),
|
||||
ymm30: r("YMM30"),
|
||||
ymm31: r("YMM31"),*/
|
||||
/*zmm0: r("ZMM0"),
|
||||
zmm1: r("ZMM1"),
|
||||
zmm2: r("ZMM2"),
|
||||
zmm3: r("ZMM3"),
|
||||
zmm4: r("ZMM4"),
|
||||
zmm5: r("ZMM5"),
|
||||
zmm6: r("ZMM6"),
|
||||
zmm7: r("ZMM7"),
|
||||
zmm8: r("ZMM8"),
|
||||
zmm9: r("ZMM9"),
|
||||
zmm10: r("ZMM10"),
|
||||
zmm11: r("ZMM11"),
|
||||
zmm12: r("ZMM12"),
|
||||
zmm13: r("ZMM13"),
|
||||
zmm14: r("ZMM14"),
|
||||
zmm15: r("ZMM15"),
|
||||
zmm16: r("ZMM16"),
|
||||
zmm17: r("ZMM17"),
|
||||
zmm18: r("ZMM18"),
|
||||
zmm19: r("ZMM19"),
|
||||
zmm20: r("ZMM20"),
|
||||
zmm21: r("ZMM21"),
|
||||
zmm22: r("ZMM22"),
|
||||
zmm23: r("ZMM23"),
|
||||
zmm24: r("ZMM24"),
|
||||
zmm25: r("ZMM25"),
|
||||
zmm26: r("ZMM26"),
|
||||
zmm27: r("ZMM27"),
|
||||
zmm28: r("ZMM28"),
|
||||
zmm29: r("ZMM29"),
|
||||
zmm30: r("ZMM30"),
|
||||
zmm31: r("ZMM31"),*/
|
||||
r8b: r("R8B"),
|
||||
r9b: r("R9B"),
|
||||
r10b: r("R10B"),
|
||||
r11b: r("R11B"),
|
||||
r12b: r("R12B"),
|
||||
r13b: r("R13B"),
|
||||
r14b: r("R14B"),
|
||||
r15b: r("R15B"),
|
||||
r8d: r("R8D"),
|
||||
r9d: r("R9D"),
|
||||
r10d: r("R10D"),
|
||||
r11d: r("R11D"),
|
||||
r12d: r("R12D"),
|
||||
r13d: r("R13D"),
|
||||
r14d: r("R14D"),
|
||||
r15d: r("R15D"),
|
||||
r8w: r("R8W"),
|
||||
r9w: r("R9W"),
|
||||
r10w: r("R10W"),
|
||||
r11w: r("R11W"),
|
||||
r12w: r("R12W"),
|
||||
r13w: r("R13W"),
|
||||
r14w: r("R14W"),
|
||||
r15w: r("R15W"),
|
||||
fpcw: r("FPUControlWord"),
|
||||
fptag: r("FPUTagWord"),
|
||||
mxcsr: r("MXCSR"),
|
||||
flags: r("flags"),
|
||||
rflags: r("rflags"),
|
||||
fip: r("FPUInstructionPointer"),
|
||||
fdp: r("FPUDataPointer"),
|
||||
fop: r("FPULastInstructionOpcode"),
|
||||
/*fds: r("FDS"),
|
||||
msr: r("MSR"),
|
||||
fcs: r("FCS"),*/
|
||||
fs_base: r("FS_OFFSET"),
|
||||
gs_base: r("GS_OFFSET"),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn get_node(&self, reg: X64Register) -> pcode::VarNode {
|
||||
match reg {
|
||||
X64Register::Rax => self.rax,
|
||||
X64Register::Rbx => self.rbx,
|
||||
X64Register::Rcx => self.rcx,
|
||||
X64Register::Rdx => self.rdx,
|
||||
X64Register::Rsi => self.rsi,
|
||||
X64Register::Rdi => self.rdi,
|
||||
X64Register::Rbp => self.rbp,
|
||||
X64Register::Rsp => self.rsp,
|
||||
X64Register::R8 => self.r8,
|
||||
X64Register::R9 => self.r9,
|
||||
X64Register::R10 => self.r10,
|
||||
X64Register::R11 => self.r11,
|
||||
X64Register::R12 => self.r12,
|
||||
X64Register::R13 => self.r13,
|
||||
X64Register::R14 => self.r14,
|
||||
X64Register::R15 => self.r15,
|
||||
X64Register::Rip => self.rip,
|
||||
X64Register::Eflags => self.eflags,
|
||||
X64Register::Cs => self.cs,
|
||||
X64Register::Ds => self.ds,
|
||||
X64Register::Es => self.es,
|
||||
X64Register::Fs => self.fs,
|
||||
X64Register::Gs => self.gs,
|
||||
X64Register::Ss => self.ss,
|
||||
X64Register::Ah => self.ah,
|
||||
X64Register::Al => self.al,
|
||||
X64Register::Ax => self.ax,
|
||||
X64Register::Bh => self.bh,
|
||||
X64Register::Bl => self.bl,
|
||||
X64Register::Bpl => self.bpl,
|
||||
X64Register::Ch => self.ch,
|
||||
X64Register::Cl => self.cl,
|
||||
X64Register::Cx => self.cx,
|
||||
X64Register::Dh => self.dh,
|
||||
X64Register::Dil => self.dil,
|
||||
X64Register::Dl => self.dl,
|
||||
X64Register::Dx => self.dx,
|
||||
X64Register::Eax => self.eax,
|
||||
X64Register::Ebp => self.ebp,
|
||||
X64Register::Ebx => self.ebx,
|
||||
X64Register::Ecx => self.ecx,
|
||||
X64Register::Edi => self.edi,
|
||||
X64Register::Edx => self.edx,
|
||||
X64Register::Esi => self.esi,
|
||||
X64Register::Esp => self.esp,
|
||||
X64Register::Fpsw => self.fpsw,
|
||||
X64Register::Gdtr => self.gdtr,
|
||||
X64Register::Idtr => self.idtr,
|
||||
X64Register::Ldtr => self.ldtr,
|
||||
X64Register::Tr => self.tr,
|
||||
X64Register::Cr0 => self.cr0,
|
||||
X64Register::Cr1 => self.cr1,
|
||||
X64Register::Cr2 => self.cr2,
|
||||
X64Register::Cr3 => self.cr3,
|
||||
X64Register::Cr4 => self.cr4,
|
||||
X64Register::Cr8 => self.cr8,
|
||||
X64Register::Dr0 => self.dr0,
|
||||
X64Register::Dr1 => self.dr1,
|
||||
X64Register::Dr2 => self.dr2,
|
||||
X64Register::Dr3 => self.dr3,
|
||||
X64Register::Dr4 => self.dr4,
|
||||
X64Register::Dr5 => self.dr5,
|
||||
X64Register::Dr6 => self.dr6,
|
||||
X64Register::Dr7 => self.dr7,
|
||||
X64Register::Fp0 => self.fp0,
|
||||
X64Register::Fp1 => self.fp1,
|
||||
X64Register::Fp2 => self.fp2,
|
||||
X64Register::Fp3 => self.fp3,
|
||||
X64Register::Fp4 => self.fp4,
|
||||
X64Register::Fp5 => self.fp5,
|
||||
X64Register::Fp6 => self.fp6,
|
||||
X64Register::Fp7 => self.fp7,
|
||||
/*X64Register::K0 => self.k0,
|
||||
X64Register::K1 => self.k1,
|
||||
X64Register::K2 => self.k2,
|
||||
X64Register::K3 => self.k3,
|
||||
X64Register::K4 => self.k4,
|
||||
X64Register::K5 => self.k5,
|
||||
X64Register::K6 => self.k6,
|
||||
X64Register::K7 => self.k7,*/
|
||||
X64Register::Mm0 => self.mm0,
|
||||
X64Register::Mm1 => self.mm1,
|
||||
X64Register::Mm2 => self.mm2,
|
||||
X64Register::Mm3 => self.mm3,
|
||||
X64Register::Mm4 => self.mm4,
|
||||
X64Register::Mm5 => self.mm5,
|
||||
X64Register::Mm6 => self.mm6,
|
||||
X64Register::Mm7 => self.mm7,
|
||||
X64Register::St0 => self.st0,
|
||||
X64Register::St1 => self.st1,
|
||||
X64Register::St2 => self.st2,
|
||||
X64Register::St3 => self.st3,
|
||||
X64Register::St4 => self.st4,
|
||||
X64Register::St5 => self.st5,
|
||||
X64Register::St6 => self.st6,
|
||||
X64Register::St7 => self.st7,
|
||||
X64Register::Xmm0 => self.xmm0,
|
||||
X64Register::Xmm1 => self.xmm1,
|
||||
X64Register::Xmm2 => self.xmm2,
|
||||
X64Register::Xmm3 => self.xmm3,
|
||||
X64Register::Xmm4 => self.xmm4,
|
||||
X64Register::Xmm5 => self.xmm5,
|
||||
X64Register::Xmm6 => self.xmm6,
|
||||
X64Register::Xmm7 => self.xmm7,
|
||||
X64Register::Xmm8 => self.xmm8,
|
||||
X64Register::Xmm9 => self.xmm9,
|
||||
X64Register::Xmm10 => self.xmm10,
|
||||
X64Register::Xmm11 => self.xmm11,
|
||||
X64Register::Xmm12 => self.xmm12,
|
||||
X64Register::Xmm13 => self.xmm13,
|
||||
X64Register::Xmm14 => self.xmm14,
|
||||
X64Register::Xmm15 => self.xmm15,
|
||||
/*X64Register::Xmm16 => self.xmm16,
|
||||
X64Register::Xmm17 => self.xmm17,
|
||||
X64Register::Xmm18 => self.xmm18,
|
||||
X64Register::Xmm19 => self.xmm19,
|
||||
X64Register::Xmm20 => self.xmm20,
|
||||
X64Register::Xmm21 => self.xmm21,
|
||||
X64Register::Xmm22 => self.xmm22,
|
||||
X64Register::Xmm23 => self.xmm23,
|
||||
X64Register::Xmm24 => self.xmm24,
|
||||
X64Register::Xmm25 => self.xmm25,
|
||||
X64Register::Xmm26 => self.xmm26,
|
||||
X64Register::Xmm27 => self.xmm27,
|
||||
X64Register::Xmm28 => self.xmm28,
|
||||
X64Register::Xmm29 => self.xmm29,
|
||||
X64Register::Xmm30 => self.xmm30,
|
||||
X64Register::Xmm31 => self.xmm31,*/
|
||||
X64Register::Ymm0 => self.ymm0,
|
||||
X64Register::Ymm1 => self.ymm1,
|
||||
X64Register::Ymm2 => self.ymm2,
|
||||
X64Register::Ymm3 => self.ymm3,
|
||||
X64Register::Ymm4 => self.ymm4,
|
||||
X64Register::Ymm5 => self.ymm5,
|
||||
X64Register::Ymm6 => self.ymm6,
|
||||
X64Register::Ymm7 => self.ymm7,
|
||||
X64Register::Ymm8 => self.ymm8,
|
||||
X64Register::Ymm9 => self.ymm9,
|
||||
X64Register::Ymm10 => self.ymm10,
|
||||
X64Register::Ymm11 => self.ymm11,
|
||||
X64Register::Ymm12 => self.ymm12,
|
||||
X64Register::Ymm13 => self.ymm13,
|
||||
X64Register::Ymm14 => self.ymm14,
|
||||
X64Register::Ymm15 => self.ymm15,
|
||||
/*X64Register::Ymm16 => self.ymm16,
|
||||
X64Register::Ymm17 => self.ymm17,
|
||||
X64Register::Ymm18 => self.ymm18,
|
||||
X64Register::Ymm19 => self.ymm19,
|
||||
X64Register::Ymm20 => self.ymm20,
|
||||
X64Register::Ymm21 => self.ymm21,
|
||||
X64Register::Ymm22 => self.ymm22,
|
||||
X64Register::Ymm23 => self.ymm23,
|
||||
X64Register::Ymm24 => self.ymm24,
|
||||
X64Register::Ymm25 => self.ymm25,
|
||||
X64Register::Ymm26 => self.ymm26,
|
||||
X64Register::Ymm27 => self.ymm27,
|
||||
X64Register::Ymm28 => self.ymm28,
|
||||
X64Register::Ymm29 => self.ymm29,
|
||||
X64Register::Ymm30 => self.ymm30,
|
||||
X64Register::Ymm31 => self.ymm31,*/
|
||||
/*X64Register::Zmm0 => self.zmm0,
|
||||
X64Register::Zmm1 => self.zmm1,
|
||||
X64Register::Zmm2 => self.zmm2,
|
||||
X64Register::Zmm3 => self.zmm3,
|
||||
X64Register::Zmm4 => self.zmm4,
|
||||
X64Register::Zmm5 => self.zmm5,
|
||||
X64Register::Zmm6 => self.zmm6,
|
||||
X64Register::Zmm7 => self.zmm7,
|
||||
X64Register::Zmm8 => self.zmm8,
|
||||
X64Register::Zmm9 => self.zmm9,
|
||||
X64Register::Zmm10 => self.zmm10,
|
||||
X64Register::Zmm11 => self.zmm11,
|
||||
X64Register::Zmm12 => self.zmm12,
|
||||
X64Register::Zmm13 => self.zmm13,
|
||||
X64Register::Zmm14 => self.zmm14,
|
||||
X64Register::Zmm15 => self.zmm15,
|
||||
X64Register::Zmm16 => self.zmm16,
|
||||
X64Register::Zmm17 => self.zmm17,
|
||||
X64Register::Zmm18 => self.zmm18,
|
||||
X64Register::Zmm19 => self.zmm19,
|
||||
X64Register::Zmm20 => self.zmm20,
|
||||
X64Register::Zmm21 => self.zmm21,
|
||||
X64Register::Zmm22 => self.zmm22,
|
||||
X64Register::Zmm23 => self.zmm23,
|
||||
X64Register::Zmm24 => self.zmm24,
|
||||
X64Register::Zmm25 => self.zmm25,
|
||||
X64Register::Zmm26 => self.zmm26,
|
||||
X64Register::Zmm27 => self.zmm27,
|
||||
X64Register::Zmm28 => self.zmm28,
|
||||
X64Register::Zmm29 => self.zmm29,
|
||||
X64Register::Zmm30 => self.zmm30,
|
||||
X64Register::Zmm31 => self.zmm31,*/
|
||||
X64Register::R8b => self.r8b,
|
||||
X64Register::R9b => self.r9b,
|
||||
X64Register::R10b => self.r10b,
|
||||
X64Register::R11b => self.r11b,
|
||||
X64Register::R12b => self.r12b,
|
||||
X64Register::R13b => self.r13b,
|
||||
X64Register::R14b => self.r14b,
|
||||
X64Register::R15b => self.r15b,
|
||||
X64Register::R8d => self.r8d,
|
||||
X64Register::R9d => self.r9d,
|
||||
X64Register::R10d => self.r10d,
|
||||
X64Register::R11d => self.r11d,
|
||||
X64Register::R12d => self.r12d,
|
||||
X64Register::R13d => self.r13d,
|
||||
X64Register::R14d => self.r14d,
|
||||
X64Register::R15d => self.r15d,
|
||||
X64Register::R8w => self.r8w,
|
||||
X64Register::R9w => self.r9w,
|
||||
X64Register::R10w => self.r10w,
|
||||
X64Register::R11w => self.r11w,
|
||||
X64Register::R12w => self.r12w,
|
||||
X64Register::R13w => self.r13w,
|
||||
X64Register::R14w => self.r14w,
|
||||
X64Register::R15w => self.r15w,
|
||||
X64Register::Fpcw => self.fpcw,
|
||||
X64Register::Fptag => self.fptag,
|
||||
//X64Register::Msr => self.msr,
|
||||
X64Register::Mxcsr => self.mxcsr,
|
||||
X64Register::FsBase => self.fs_base,
|
||||
X64Register::GsBase => self.gs_base,
|
||||
X64Register::Flags => self.flags,
|
||||
X64Register::Rflags => self.rflags,
|
||||
X64Register::Fip => self.fip,
|
||||
//X64Register::Fcs => self.fcs,
|
||||
X64Register::Fdp => self.fdp,
|
||||
//X64Register::Fds => self.fds,
|
||||
X64Register::Fop => self.fop,
|
||||
_ => panic!("Unsupported register"),
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user